Generate 1Hz clock from a 50MHz clock

[Altera_Forum]

I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. 

I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as enable.   And I have saw some posts said that the most straighforward way is to generate a 1Hz clock by using a counter: toggle the 1Hz clock every 20_000_000 cycles of the 40Mhz clock. (no. 21981)   However, this method will require a large counter (25 bits or so) running at 40 Mhz. I have another idea that to use some smaller counter to generate the 1Hz clock: firstly to generate a 400K clock by using a smaller counter of 6 bit (range from 1 to 50), then use another counter to generate a 4KHz clock, then to generate 40HZ clock, then to 1Hz clock. This method needs three counter of 6bit (range from 1 to 50) and one 5bit counter (range from 1 to 20).   Can anyone help to tell what difference between the two methods (one large counter, some smaller counters)? Which method is more efficient in using CPLD's resources (LE, LUT, etc.)   ps. i am working in VHDL.

[Altera_Forum]

I would rather use 25 bits and avoid the analysis of cascaded counters. 

You are not counting the overheads of each division which needs a toggle signal per stage as well as logic to detect the max count.  note also that cpld hasn't got LUT as fpga

[Altera_Forum]

Oh and count down instead of counting up. 

It's simpler to detect that underflow.

[Altera_Forum]

kaz, 

 MAXII actually has a LUT-architecture! (see page 2-8 of the MAX II Device Handbook).  ghxy00,  The issue with long counters is that even the fast carry chain tends to take longer. Cascading 8-bit lpm counters using a look-ahead register carry-over to the next counter will generate the fastest counter. Actually I am working on a StratixII GX EP2SGX60F1152-C3 design where I have trouble with a 24 bit counter running at 100 MHz!  So I amused myself a bit and made a small test-project for a (slower) MAXII EPM240ZM68C7 device (see attached .qar). I got 44.98 MHz for a standard LPM based design, and got 102 Mhz for the cascaded LPM version. This comes of course with a price; you will use more LUTs. Design settings were : Analysis set to Speed and fitting to Standard Effort.

[Altera_Forum]

to amilcar, 

 I don't think (in fact I'm almost sure) counting down makes a difference, you need all bits to do a comparison anyway?

[Altera_Forum]

--- Quote Start ---  kaz,  MAXII actually has a LUT-architecture! (see page 2-8 of the MAX II Device Handbook).    --- Quote End ---    Thanks for letting me know. I wonder why these manufacturing people keep changing things and making our life at field a bit hard. I assume the cpld arhitecture based on sum of produts is meant to be very fast so why did they steal from fpga's LUT??

[Altera_Forum]

Fast isn't one of the adjectives I'd use for traditional CPLDs. Nor flexible. 

MAX II are generally faster and much more capable than MAX x000 series.

[Altera_Forum]

--- Quote Start ---  I wonder why these manufacturing people keep changing things and making our life at field a bit hard.  --- Quote End ---   Although offered as a "CPLD", MAXII is actually a family of small SRAM based FPGAs with nonvolatile configuration. I assume, it's the only way to achieve a similar logic complexity. I won't expect a typical small CPLD design to be slower with MAX II.   Unfortunately, josyb's test code doesn't work with MAX3000 CPLD, Quartus says to use latches and doesn't give a meaningful timing analysis.

[Altera_Forum]

--- Quote Start ---  kaz,   MAXII actually has a LUT-architecture! (see page 2-8 of the MAX II Device Handbook).   ghxy00,   The issue with long counters is that even the fast carry chain tends to take longer. Cascading 8-bit lpm counters using a look-ahead register carry-over to the next counter will generate the fastest counter. Actually I am working on a StratixII GX EP2SGX60F1152-C3 design where I have trouble with a 24 bit counter running at 100 MHz!  So I amused myself a bit and made a small test-project for a (slower) MAXII EPM240ZM68C7 device (see attached .qar). I got 44.98 MHz for a standard LPM based design, and got 102 Mhz for the cascaded LPM version. This comes of course with a price; you will use more LUTs. Design settings were : Analysis set to Speed and fitting to Standard Effort.  --- Quote End ---     It's true that more logic elements are used. I have compare two kinds of counters: one 22bit large counter to four 5bit small counter. The used LE are respectively 31 to 28. (please attached source code and summary info files).   Unfortunately, in the design with cascaded counters, the ripple clocks are generated. How to remove such warning?

[Altera_Forum]

To josyb, 

 Yes, you are probably right, because the overflow value is fixed at compile time, counting up or down should not make a difference. But for other cases it does, so I try to always count down, that way if I latter want to change the design to be a bit more dynamic then I do not have that many changes to make and I still get optimal results.

[Altera_Forum]

ghxy00, 

 you are actually creating ripple clocks in your design, so it is a fair warning you get. You can avoid the ripple clock warning by using the global 50 MHz clock for all cascaded counters and use the carries from the previous chain as enables for the dollwing chain. But if you do that by simple combinatorial logic you will get a slower counter again. That's why I used registered look-ahead carries in my example.