Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16612 Discussions

Gate-level netlist simulation with Modelsim

Altera_Forum
Honored Contributor II
1,178 Views

Hi all, 

I just completely built gate-level netlist, using Buildgate tool of Cadence. Now, I want to simulate this netlist to compare to RTL coding. Could you show me how to do this (step by step, please)? 

Many thanks
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
371 Views
0 Kudos
Reply