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How to constrain output for SRAM in TimeQuest?

Altera_Forum
Honored Contributor II
‎05-10-2010 01:48 PM
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There are examples about source synchronous design such as SDRAM time constrain, but I wonder how to constrain output for SRAM in TimeQuest? 

eg. no clock needed for SRAM, but you must point a clock in the Set Output/Input Delay setup.  

The SRAM data is changed with SRAM address latch in read process, but is it right to set the address as clock? 

Thanks very much!
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Altera_Forum
Honored Contributor II
‎05-10-2010 01:54 PM
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There should be a write_enable that does the write, so for writes I consider that the clock and constrain address/data in relation to it.

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