qxp file issues

[Altera_Forum]

Hi, 

I am having a problem in Quartus with the .qxp files that I need to generate. Currently I have a project in Quartus which is 100% complete, simulated, fully constrained and meets timing and all the rest. I need to pass this design to another group as they need to add their modules to it. The problem is that they are not allowed to see my VHDL source code, which is making life a little difficult.   I have been reading the quartus ii incremental compilation for (http://www.altera.com/literature/hb/qts/qts_qii51015.pdf) hierarchical and team-based design (http://www.altera.com/literature/hb/qts/qts_qii51015.pdf) handbook to get some help. What I am doing is generating a qxp file for each component in the design. I have a project layed out as follows: Top Level Interface to control interface 1 Interface to control interface 2 Interface to control interface 3 Interface to control interface 4  What I have done is set each of the lower level components as the top level, compl¡led the design and exported it as a design partition. I repeat this for all 4 lower level components. Then I remove the original VHDL files from the project and add the 4 qxp files. When I compile the design again with the original top level as the top level (and instaiating the components as before), it seems that the component 1 works as expected on the board, but the remaining components do not. Upon closer inspection, I noticed that during the compilation process it was ignoring some of the 'create clock' statements in my .sdc file and these clocks as it happened are used in the components which do not work. I cannot understand why it gives me this problem for only certain components.   Anyway, could someone please advise me as to whether this approach is the best way to achieve what i am trying to do. If it is not the most efficient way or I am not doing it correctly please advise.   I was playing around with partitions, and after creating a partition for the respective components, and enabling incremental compilation, it starts giving me fatal errors, which i haven´t fully understood yet. I am obviously doing something badly worng. I´d be very grateful for any help.   Many thanks

[Altera_Forum]

--- Quote Start ---  Hi, I am having a problem in Quartus with the .qxp files that I need to generate. Currently I have a project in Quartus which is 100% complete, simulated, fully constrained and meets timing and all the rest. I need to pass this design to another group as they need to add their modules to it. The problem is that they are not allowed to see my VHDL source code, which is making life a little difficult.   I have been reading the quartus ii incremental compilation for (http://www.altera.com/literature/hb/qts/qts_qii51015.pdf) hierarchical and team-based design (http://www.altera.com/literature/hb/qts/qts_qii51015.pdf) handbook to get some help. What I am doing is generating a qxp file for each component in the design. I have a project layed out as follows: Top Level Interface to control interface 1 Interface to control interface 2 Interface to control interface 3 Interface to control interface 4  What I have done is set each of the lower level components as the top level, compl¡led the design and exported it as a design partition. I repeat this for all 4 lower level components. Then I remove the original VHDL files from the project and add the 4 qxp files. When I compile the design again with the original top level as the top level (and instaiating the components as before), it seems that the component 1 works as expected on the board, but the remaining components do not. Upon closer inspection, I noticed that during the compilation process it was ignoring some of the 'create clock' statements in my .sdc file and these clocks as it happened are used in the components which do not work. I cannot understand why it gives me this problem for only certain components.   Anyway, could someone please advise me as to whether this approach is the best way to achieve what i am trying to do. If it is not the most efficient way or I am not doing it correctly please advise.   I was playing around with partitions, and after creating a partition for the respective components, and enabling incremental compilation, it starts giving me fatal errors, which i haven´t fully understood yet. I am obviously doing something badly worng. I´d be very grateful for any help.   Many thanks  --- Quote End ---    Hi,  did you define your components as design partitions in your toplevel project ? Did you generate clocks inside your imported components ?  Kind regards  GPK

[Altera_Forum]

Hi pletz, 

Thanks for the reply. I am not generating clocks inside the imported components. All clocks enter via the device pins and there is a pll in the top level which also genterates a clock.   In my top level project, I may have incorrectly defined the components as design partitions. I right clicked on the component in hierarchy window and and clicked set as design partition. I was unsure as to how to do this, so what I did was instantiate the component while the vhdl files or .qxp files was not included in the project, then ran synthises, it produced an error, and then was able to right click it. Without doing this the component didn´t show up in the hierarchy window. I am sure there must be a better way to do this.   I am successfully able to instantiate one component this way, but when I add the 2nd, when it does the timing analysis, quartus produces a fatal error and stops. i would be very gratful if you could tell me what i am doing wrong.   Thanks again

[Altera_Forum]

This is the fatal error that appears when I import two partitions and compile: 

 *** Fatal Error: Access Violation at 0X0030249D Module: quartus_sta.exe Lock in use: 9 Stack Trace:  0x249d: mem_is_allocated + 0xd (ccl_mem)  0xc0c4: PDB_SEGMENT_WRITER::xfr_ptr + 0x14 (DB_PDB)  0xbf6aa: HDB_SOURCE_FILE::operator<< + 0x15a (DB_HDB) End-trace    Any help would be greatly appreciated. Thanks

[Altera_Forum]

--- Quote Start ---  This is the fatal error that appears when I import two partitions and compile:   *** Fatal Error: Access Violation at 0X0030249D Module: quartus_sta.exe Lock in use: 9 Stack Trace:  0x249d: mem_is_allocated + 0xd (ccl_mem)  0xc0c4: PDB_SEGMENT_WRITER::xfr_ptr + 0x14 (DB_PDB)  0xbf6aa: HDB_SOURCE_FILE::operator<< + 0x15a (DB_HDB) End-trace    Any help would be greatly appreciated. Thanks  --- Quote End ---    This is probably a quartus bug rather than a problem with what you are trying to do. Report it via mysupport.

[Altera_Forum]

Ok thanks, I have submitted a request to Altera. 

 But also please confirm for me, if the way I am doing this seems ok. I tried to follow the document, but I am hoping that I have not misinterpreted something.  Thanks again.

[Altera_Forum]

--- Quote Start ---  Ok thanks, I have submitted a request to Altera.  But also please confirm for me, if the way I am doing this seems ok. I tried to follow the document, but I am hoping that I have not misinterpreted something.  Thanks again.  --- Quote End ---    Hi,  which version Quartus do you use ? Quartus 9.1 SP2 ? If not, try this version.  When you generate your qxp file what netlist did you use . Post-fit or post-synthesis ?  Kind regards  GPK

[Altera_Forum]

Hi again, 

I didn´t have quartus updated with SP2. I am currently downloading it and will report back on whether things improve.   When I generate the .qxp file I generate a post synthesis netlist. I didn´t generate a post fitting netlist as the othe rteam have to put their part of the design on the FPGA and I wanted to leave things more flexible. Should I have used a post fitting netlist? Would this improve things and why?   Thansk again for the help.

[Altera_Forum]

--- Quote Start ---  Hi again, I didn´t have quartus updated with SP2. I am currently downloading it and will report back on whether things improve.   When I generate the .qxp file I generate a post synthesis netlist. I didn´t generate a post fitting netlist as the othe rteam have to put their part of the design on the FPGA and I wanted to leave things more flexible. Should I have used a post fitting netlist? Would this improve things and why?   Thansk again for the help.  --- Quote End ---    Hi,  in your case is the synthesis netlist the right choice, as long as you don't need e.g. placement for preserving the timing. In your first post you mentioned that some of your "create_clock" assignment are ignored. Can tell a little more about this issue ?  Kind regards  GPK

[Altera_Forum]

Hi pletz, 

Regarding the create clock statements. I have one .sdc file for the entire project where all timing constraints are in place for timequest. When I compile my project normally (without using qxp files) everything works fine, no create clock statements are ignored and the design works perfectly on the board.   What I then did was set the respective components as the top level and ran the compilation. It gave quite a few warnings regarding ignored constraints which I figured was normal as I was only compiling one component and it sub components rather that the entire design.   When I import the qxp files for some of the components and re run the complilation for the entire project, it tells me that certain create clock commands were ignored. I am using the same .sdc file as for the compilation without .qxp files. This happened before I set the components as partitions and with incremental compilation turned off. When this occured, I just added the qxp file to the project and instantiated as normal. It compiled successfully but did not work and ignored certain create clock commands (but not all).    Now with the components specified as a partition, and incremental compilation turned on, it does not get far enough to do the timing analysis as it produces a fatal error.   I´m not sure if what I was doing before is correct and therefore the create clock ignored issue may not have been a serious issue   Many thanks for the help so far

[Altera_Forum]

--- Quote Start ---  Hi pletz, Regarding the create clock statements. I have one .sdc file for the entire project where all timing constraints are in place for timequest. When I compile my project normally (without using qxp files) everything works fine, no create clock statements are ignored and the design works perfectly on the board.   What I then did was set the respective components as the top level and ran the compilation. It gave quite a few warnings regarding ignored constraints which I figured was normal as I was only compiling one component and it sub components rather that the entire design.   When I import the qxp files for some of the components and re run the complilation for the entire project, it tells me that certain create clock commands were ignored. I am using the same .sdc file as for the compilation without .qxp files. This happened before I set the components as partitions and with incremental compilation turned off. When this occured, I just added the qxp file to the project and instantiated as normal. It compiled successfully but did not work and ignored certain create clock commands (but not all).    Now with the components specified as a partition, and incremental compilation turned on, it does not get far enough to do the timing analysis as it produces a fatal error.   I´m not sure if what I was doing before is correct and therefore the create clock ignored issue may not have been a serious issue   Many thanks for the help so far  --- Quote End ---    Hi,  I always setup separate Quartus projects for the parts I would like to import. Maybe you can try it out.  Kind regards  GPK

[Altera_Forum]

Hi again, 

I updated to Quartus 9.1 SP2 and everything is now working correctly. I was suprised at this. Beforehand I was using v9.1 without any sevice pack.   For now everything seems to be in order. I´ll post back if anything else unexpected happens.   many thanks for all the help

[Altera_Forum]

I also got a speedy reply from Altera mysupport on this, shown below. 

I had things working with my old approach after installing service pack 2 but have now used their recomended approach which was slightly different and it is also working, so I will adopt this approach.   Here is the response from teh Altera expert, in case anyone else has a similar issue in teh future:     --- Quote Start ---  I have referred to your post on the Altera Forum and my only comment is the toplevel is supposed to act as a wrapper for the lower level modules, you therefore need to compile each lower level module in the full design, and export each in turn from the full compilation but with the modules left blank or black boxes.  For example create 4 separate projects.  Project 1  Top Level (wrapper) Interface to control interface 1 (source code) Interface to control interface 2 (leave empty) Interface to control interface 3 (leave empty) Interface to control interface 4 (leave empty)  Then export the partition for interface 1.  Like wise.  Project 2  Top Level (wrapper) Interface to control interface 1 (leave empty) Interface to control interface 2 (source code) Interface to control interface 3 (leave empty) Interface to control interface 4 (leave empty)  Then export the partition for interface 2.  Continue this for all 4 modules.  Your final project will now be as followings.  Top Level (wrapper) Interface to control interface 1 (imported QXP) Interface to control interface 2 (imported QXP) Interface to control interface 3 (imported QXP) Interface to control interface 4 (imported QXP)  This is covered in the Incremental compilation QII handbook.  http://www.altera.com/literature/hb/qts/qts_qii51015.pdf  --- Quote End ---  

[Altera_Forum]

Hi again, 

Just one final question with regard to this issue. I have sucessfully compiled my partitioned design but in certain partitions, I have some ports which are unused at the moment. They seem to appear as dangling ports in the pin planner even though they are not actual I/O´s. Could someone explain to me what a dangling port is? an unused one?   Also they are interfering with timequest and it is complaining of 100´s of unconstrained paths, even though the design was fully constrained before partitioning. UJpon inspection they are mostly due to dangling ports.   I would be grateful if someone could let me know the best way to deal with dangling ports and explain exactly how they come to be?   Many thanks for the help.

[Altera_Forum]

--- Quote Start ---  Hi again, Just one final question with regard to this issue. I have sucessfully compiled my partitioned design but in certain partitions, I have some ports which are unused at the moment. They seem to appear as dangling ports in the pin planner even though they are not actual I/O´s. Could someone explain to me what a dangling port is? an unused one?   Also they are interfering with timequest and it is complaining of 100´s of unconstrained paths, even though the design was fully constrained before partitioning. UJpon inspection they are mostly due to dangling ports.   I would be grateful if someone could let me know the best way to deal with dangling ports and explain exactly how they come to be?   Many thanks for the help.  --- Quote End ---    Hi,  when you define a design partition Quartus preserves the interface of the partition. Unused ports are no longer removed. If you e.g. have outputs which are not used , they will be left as dangling ports in your desgin. If it is ok that they are not used you can ignore the dangling ports. Keep also in mind that no cross-partition optimization takes place, that could lead to unused inputs or inputs which are stucked to "1" or "0".  Kind regards  GPK

[Altera_Forum]

Thanks for the reply pletz. 

Is there anyway to prevent the dangling ports from appearing in the pin planner. It´s just that i have to pass my part of the design onto another group and it just looks a bit untidy that they appear there when there are not really inputs and outputs. I tried simply deleting them but they reappear after the next compilation.   I understand that they are nothing to worry about but would be interested to know if there is a simple way to prevent them from appearing in the pin planner.     Manya thanks again,

[Altera_Forum]

--- Quote Start ---  Thanks for the reply pletz. Is there anyway to prevent the dangling ports from appearing in the pin planner. It´s just that i have to pass my part of the design onto another group and it just looks a bit untidy that they appear there when there are not really inputs and outputs. I tried simply deleting them but they reappear after the next compilation.   I understand that they are nothing to worry about but would be interested to know if there is a simple way to prevent them from appearing in the pin planner.     Manya thanks again,  --- Quote End ---     Hi,  it surpised me that you could see the internal dangling port in the pin planner. My understanding was that you could see only ports of your design in the pin planner. I never saw internal signals in the planning tool ????  Kind regards  GPK