MAX II reprogramming cycles?

[Altera_Forum]

Hello guys. 

 I am wondering what the "erase and reprogram cycles" of 100, that is stated for the Altera MAX II CPLD, physically mean.   Does this mean I can only program a source code into the device for 100 times?  Or don't I use the UFM and CFM blocks every time when I program a basic source code?   If this is really the programming of every kind of code, the number of 100 really is an issue. I bought a dev. kit for this CPLD to help me understand VHDL and just play around with it, so 100 chances aren't that great...

[Altera_Forum]

you're right, you can only erase the MAXII's internal flash up to 100 times to still be in the operating specs. in a non-production environment you can probably push it out past 100 erases, but you may want to think about getting a small FPGA dev kit which is SRAM based. an FPGA won't have the same issue with erases as CPLD flash memory.

[Altera_Forum]

Bummer, that's really a con! 

The kit cost me about 70 pounds... :(   What set with a FPGA (not with too much additional stuff like LCD etc.) would you advise?

[Altera_Forum]

if you want to go very low cost there is an eBay seller that has a kit with a Cyclone II 5 kLE device and an EPCS configuration device. i am not the seller nor have i tried the board, but its one of the cheapest way to get an Altera FPGA dev kit. you'd have to add any peripherals (LED, 7-seg, LCD, switches, etc).