Help me about measure clock on osciloscope.

[Altera_Forum]

Hi everyone, 

I have project on board DE2. I use PLL in megafunction to create the clock 500MHz from 50MHz. Then i use clock counter to decrease the clock from 500MHz to clock_out 250KHz, 125KHz, 60KHz.... and the clock_out is mapped to pin GPIO_1[0]. I use osciloscope to measure frequency of clock_out, but i can not see the the pulse ( square pulse), it only show the line . anybody know why? Thanks.

[Altera_Forum]

why do you create a 500MHz clock? cant you derrive your other clocks from the 50MHz one?

[Altera_Forum]

That's right, but my project is design optimization .I must create 500MHz, 250MHz, 125 MHz... but this clock can't be measured in oscilloscope ,so i must divide this clock again. that means (250MHz <-> 250KHz, 125MHz <->125KHz...onty to show corelative clock).

[Altera_Forum]

500MHz is rather fast. Did it pass timing requirements?

[Altera_Forum]

I tested my design , 500MHz my design failed, but smaller 250MHz is ok.  

I also mapped clock_out to the LEDR[0] for testing, when i use switch to change clock_out the LEDR[0], the speed blink of LED also changed, it proved that the clock_out had change. "Did it pass timing requirements?" -> what u mean? require on osci or on design.:d

[Altera_Forum]

Actually, the clock that i create very small value, about under 50KHz. I'm afraid that can the bi-direction (inout) GPIO be measured on osci?

[Altera_Forum]

GPIO signals can be seen in a oscilloscope. 

However, anything faster than a few tens of MHz is going to be seriously distorted.  Tricky was asking you if you have run your design though TimeQuest to make sure it works correctly with the clocks.

[Altera_Forum]

butxarakham.nh2008  

you should first learn and use the TimeQuest tool in your design. After this you have to certify if you are using the correct bank of I/O (if this clock is permitted for this family).  sds[]

[Altera_Forum]

I will try. 

Thanks for your kindness!!! :d

[Altera_Forum]

I understand, that you already did some basic timing checks with your design, as you reported it "failed at 500 MHz". The classical timing analyzer would be sufficient for this simple purpose. You can also expect, that Quartus doesn't allow assignment of "unreachable" pins or similar. In so far, only a few basic issues, that can't be checked by Quartus, may explain the said problem: 

 - you specified a clock input, that isn't actually connected to a DE2 clock oscillator - you send the output to a Cyclone II pin other than connected to the expected GPIO - you generated an output signal, that's too short to be viewed by your equipment - you didn't manage to downlöoad the correct configuration - your DE2 board isn't working correctly  Please apologize that I consider such basic issues, but they happen every day.

[Altera_Forum]

Thank all! I can do that. 

I have a new problem.!!! Can we divide clock by 3,5,6... ??? i mean that if i have 500MHz can i create clock out 166,7 MHz? ( fout = 1/3f )

[Altera_Forum]

If you use a phase-lock loop - yes 

 Dont bother if you're tryimng to create it using counters - that goes for any clock in the MHz range.

[Altera_Forum]

I understand, i used pll with inclk0 = 50MHz and 2 output clock that 500, 400MHz. Can u tell me why i can not create the second output clock 400MHz??? it said that : 

"Cannot implement the request PLL". "Cause : Request mult/div factor not achievable". And the output clock parameter : mul = 20 , div = 3 why???(50*20/3 != 400MHz) if right , they must be mul = 8, div = 1 because 50MHz * 8 = 400.