Quartus II Simulator

Altera_Forum · ‎05-15-2010

Hello,

I've recently started using Quartus II Web edition and there's something I don't understand :

- I use a .vwf file to simulate a design,

- I insert a node and open 'Node finder' to search for nodes;

- then I add some node named tmp_test (that appears in the 'nodes found' list on the node finder) and click the OK button;

- back to the Quartus main window, I click on 'Start Simulation' and there are some warnings which tell that Quartus can't find the node :

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[7]" in design.

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[6]" in design.

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[5]" in design.

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[4]" in design.

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[3]" in design.

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[2]" in design.

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[1]" in design.

Warning: Ignored node in vector source file. Can't find corresponding node name "PCM3006:inst6|tmp_test[0]" in design.

I've tried to find the reason of this but still haven't found the answer... Could someone help please ?

Thanks !

Altera_Forum · ‎05-16-2010

Quartus Simulator as well as SignalTap II have problems to tap signals, that don't physically exist in the design, e.g. because they are only a wire signal respectively an alias of a different signal. As a general rule, try to tap each signal at it's source, in the design entity where it's generated.

Some signals are possibly completely removed during design optimization. They can't be tapped at any place.

Altera_Forum · ‎05-16-2010

Hello FvM, what do you mean by "tap each signal at its source" ? For example, in one VHDL entity I've got the following signal that I'd like to monitor on the quartus simulator :

signal tmp_test : unsigned (7 downto 0);

My design consists in one 'block diagram/schematic' file and a VHDL file (where is defined the tmp_test signal).

The only way I've found to monitor that 'tmp_test' signal is to output the signal to the schematic with a conversion using std_logic_vector and connecting that vector to output pins.

This is not too hard in a very simple project but in a more complex one this technique might be impossible.

Thanks.

Altera_Forum · ‎05-16-2010

What is the source of this signal (Register, combinational logic)? Are you sure, that the signal is actually existing in the compiled design? If no design output depends on it (directly or indirectly), it will be removed during design optimization.

Altera_Forum · ‎05-16-2010

In the 'Node finder' the signal tmp_test only appears when filter is set to design entry. It doesn't appear in post-compilation. tmp_test is sourced from an unsigned and no output depends on it. This is the VHDL code :

ARCHITECTURE PCM3006_architecture OF PCM3006 IS

SIGNAL NEW_COUNT, COUNT : UNSIGNED (7 DOWNTO 0);

SIGNAL TMP_TEST : STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

NEW_COUNT <= (COUNT+1)MOD 256;

TMP_TEST <= STD_LOGIC_VECTOR(COUNT);

SYNC : PROCESS (CLK)

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

COUNT <= NEW_COUNT;

END IF;

END PROCESS;

END PCM3006_architecture;

tmp_test, count and new_count are removed after compilation.

Altera_Forum · ‎05-16-2010

--- Quote Start ---

tmp_test, count and new_count are removed after compilation

--- Quote End ---

Yes, they aren't independant signals, that actually exist in the design. As you have an assignment tmp_test <= std_logic_vector(count); in concurrent code, temp_test isn't but an alias of count. Displaying count in the simulator has the same result.

Altera_Forum · ‎05-17-2010

A few of things?

Why dont you just have this code instead of using an asynchronous "new_count" signal? The following code is much more readable:


SYNC : PROCESS (CLK)
    BEGIN
         IF (CLK'EVENT AND CLK='1') THEN
              COUNT <= COUNT + 1;
END IF;
    END PROCESS;

Secondly, does tmp_test connect to any output?

Thirdly, if they dont connect to any outputs, no wonder they dont exist. The synthesiser gets rid of any unnessasary logic (which is what this will be if not connected to an output). You can stop this process however, by using the attribute "noprune" like this:


attribute noprune : boolean;
attribute noprune of COUNT : signal is true;

That way, COUNT wont be synthesised away.

Altera_Forum · ‎05-17-2010

I'm just starting learning VHDL and FPGA's and my piece of code comes from a tutorial example. But I agree with you, its needlessly complicated. tmp_test is not connected to any output, I understand now why it's impossible to watch it on the simulator. Thanks for the 'norpune' hint, it will help me for future !!

Altera_Forum · ‎05-17-2010

By the way, I've got another question concerning the simulator. The 'time' axis (in .vwf file) stops at 1us and I just don't understand how to increase the higher limit to more than that... ? I have a clock signal defined in the .vwf file, and I set the value to value>Clock... > Time range from 0ps to 5us and Quartus displays 'Specify a legal end time'... So I can't go over 1us...

Altera_Forum · ‎05-17-2010

Best thing to do is stop using the quartus simulator and use modelsim instead. The quartus simulator is very limited, and is being discontinued from Quartus 10.

Altera_Forum · ‎05-17-2010

Ok, I was expecting that answer... :) ... thanks...