FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

Avalon-MM burst mode uniphy

Altera_Forum
Honored Contributor II
997 Views

Hello! I try to use altera reference disign multiport frontend with different burst size in ports; 

I dont completely understand how works burst addressation. 

For example : i use data wingth 256 bit => master_addr = {user_addr,5'b0}; 

 

i write burstsize = 2 in address =7 => master_addr = 00E0; data - d(1)='.....e1' d(2)='....e2' byteenable = ffffffff; 

how i understand in this case d(1) write in addr=7 (00E0) and d(2)write in addr =8(0100)? correct? 

 

 

after that a write burstsize = 1 in addr = 8 data - 'e6' 

 

after that i read burstsize = 2 in addr = 7 and i get 'e1' 'e2'. I thought i will get 'e1' 'e6'. where i wrong?
0 Kudos
0 Replies
Reply