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Hi all!
I just wrote a vhdl core that has only one output signal, 48-bits wide, called 'mac'. I used the component editor in order to generate a _hw.tcl file and to use this core in SOPC builder. The component corresponding to my core has an Avalon-ST source interface, with only a data signal: mac. There are no ready, valid, sop, eop, empty or error signals in this Avalon-ST interface. This is compliant with the Avalon Interface Specification. The data is considered valid each clock cycle. I also created another core with a similar Avalon-ST sink. Then I instanciated these cores (src_core and dst_core) in a system and connected them together. There was no error nor warning during elaboration nor generation. But in the resulting system: - output 'mac' of src_core is connected to a signal that is not used - the system entity has a 48-bits input called 'mac' that I did not specify - input 'mac' of dst_core is connected to this system top-level input Anyone knows why that is? And how to effectively connect src-core and dst-core with an Avalon-ST bus composed of only a data signal? Thx JulienLink Copied
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I did it all again and this issue did not occur again... Must have been a bug when I ran the component editor the first time...
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