Video deinterlacing with sopc builder

[Altera_Forum]

Hello all, 

I need help about deinterlacing using Video processing in SOPC builder, without the use of external memory.    I have done a simple project with:  Test pattern generator -> deinterlacer -> clocked video output    Test pattern generator is configured as 800x600, RGB, interlaced (F1 first); deinterlacer is configured as 800x600, F1 as default initial field, Bob-scanline duplication as deinterlacing method (no buffering); clocked video output is configured as 800x600, 800 pixels fifo size, 0 pixel for fifo level at which to start output, and appropriate horizontal and vertical sync.  The output video clock is 35.8MHz.    When I look at the output video, the video is shifted horizontally and vertically...    What can be wrong?    (When I add a frame buffer after the deinterlacer, the video is correctly displayed, but I think it can be possible not to use a frame buffer…)    Thanks in advance,

[Altera_Forum]

Hi, 

 It is perhaps not related to the problem you are seeing but you should use something greater than 0 for "fifo level at which to start output" in the CVO. You would be less likely to underflow the output. 400 would be reasonable since your FIFO size is 800.

[Altera_Forum]

Thanks, I have changed the fifo level at which to start output, but it has not solved the problem. 

If someone has a new suggestion, it would be nice. I really don't understand why the video is shifted... Thanks

[Altera_Forum]

Are you using synchronize on F1 or synchronize on F0? If yes then I believe this system does not work because the deinterlacer is discarding every other field and uses only F0s (or F1s) to generate progressive frames. 

 This would mean that the deinterlacer cannot avoid a huge gap between two successives output frames and that your output is underflowing. This would also explain why this system is working with a frame buffer. Switching to synchronize on both may fix the problem.

[Altera_Forum]

Thanks for your help, but I have found the problem: 

I might seems logical, but the SOPC builder must be clocked with the pixel clock, whereas I was using a faster clock. I'm a little bit surprised, because I thought the avalon bus needed a faster clock in order to transmit pixels and some others data in real time... and I thought that vid_clk at CVO was used to regenerate the correct video flow. (and that's why it worked fine with frame buffer).  Thanks anyway!

[Altera_Forum]

--- Quote Start ---  I might seems logical, but the SOPC builder must be clocked with the pixel clock, whereas I was using a faster clock. I'm a little bit surprised, because I thought the avalon bus needed a faster clock in order to transmit pixels and some others data in real time... and I thought that vid_clk at CVO was used to regenerate the correct video flow.  --- Quote End ---  The reason you can get away with using the pixel clock in some cases is because of the horizontal blanking interval. The average data rate for a line is actually a little less than the pixel clock.  However, I suspect you may still have some other issue in your system. You should be able to use an independent faster clock for the VIP components.