Top module logic utilization lesser than sub-modules

[Altera_Forum]

Just created a Verilog top-level module which instantiates about 10 sub-modules. When I wrote those individual sub-modules each of them took about 5%-6% of logic utilization. My estimate was that the final top-module would take somewhere around ~60% of logic utilization. Strangely when setting the top-level module as top-level module and compiling it, the logic utilization for this module shows only 2%. Why is this like this? I'm confused by this. Any help is most appreciated. Thanks.

[Altera_Forum]

The tools are able to optimize each instance of each module. 

And sometimes, minor bugs can cause modules to be optimized away almost entirely.   Ie, let's say that you have a submodule with a reset input. Now let's say that you have a bug in your top level module that causes that submodule's reset signal to be a constant "1".  The tools will be, more or less, be able to see that and will reduce the submodule to almost nothing,

[Altera_Forum]

Thanks rbugalho, how can I see what modules are being optimized away. I guess that also means that I need to run simulations to find out what the bug in the top level module is and then fix the bug to see true logic utilization. However does anything come into your mind off the top of your head, because none of my submodules are custom, all are using altera floating point cores. Can you think of any signal(s) which might be causing them to be optimized away? Thanks again for your reply.

[Altera_Forum]

You can look at the synthesis report to see what was synthesized away. Most common reasons for this are: 

 1 - You didn't connect the clock. 2 - You don't have any outputs dependent on the module outputs. If the logic of your modules to feed anything useful (like I/O) the whole thing gets optimized away. This happens all the time when people are trying to compile projects for size estimates.  Jake

[Altera_Forum]

@jake, Thanks. Right now Quartus shows most of the submodules as synthesized away. But individually all the sub-modules when compiled as the top-level module show 6%-7% logic utilization. Would I be correct in inferring then that the problem doesn't lie in the definition of the sub-modules rather it is the issue of non-utilization of generated signals from the submodules in the top-level module?

[Altera_Forum]

That would certainly fit under item number 2 in my previous post. 

 Jake