Code Coverage

[Altera_Forum]

Hello Friends, 

 I want to enable Code Coverage option of my modelsim. I m using altera Modelsim 6.5b. Also compilation option is disable,so i want to enable this option also. if any one have any idea then give me your reviews.  Thank in Advance.....

[Altera_Forum]

IIRC Code coverage isn't available in Altera Modelsim (well the option is in the menu, but always disabled). You need at least to buy Modelsim PE + code coverage option, or Modelsim DE/SE.

[Altera_Forum]

Thank You.... 

Do you have idea about verification methods? i want to know complete verification flow as all MNC used for ASIC/FPGA. if i want to verify parallel to serial converter module then what should be my steps for design complete verification environment?  Thanks in Advance.......

[Altera_Forum]

--- Quote Start ---  Thank You.... Do you have idea about verification methods? i want to know complete verification flow as all MNC used for ASIC/FPGA.   --- Quote End ---    For ASIC Verification methods, refer to forums like www.vmmcentral.org, www.ovmworld.org and www.uvmworld.org - recently Accellera released UVM EA version that is expected to be used by major ASIC houses few years down (I already am working with few local customers starting with it here in India).   You also have online/printed books on these topics.   To start with you should pick up SystemVerilog and then move onto methodologies.     --- Quote Start ---   if i want to verify parallel to serial converter module then what should be my steps for design complete verification environment?   --- Quote End ---   But believe me - it is not that entire world is SystemVerilog, fundamentals of functional verification remain the same regardless of these advanced technologies and languages. Sure these methods help you do better, faster and more. To start with you go through this PDF:   http://www.cvcblr.com/trng_profiles/cvc_in_cfv_profile.pdf   If you can decipher each topic one by one (you may start with a small design like parallel-to-serial converter like you said), then you are fine. You seem to be on right track - look at code coverage, add more checkers, understand closure, regressions.  If you are a student (in any reputed college in India), consider joining our BUDS internship http://www.cvcblr.com/downloads/buds_cvc_acad.pdf where-in we guide you through this process on sample projects for FREE - but you need to do all the hard work. We have 3 successful teams working with us from KLU in TamilNadu (India) and doing things like AHB, APB design & verification - all B.E. ECE students.

[Altera_Forum]

Thanks.... 

 I m not student. I m working as IP Design Engineer, I have 2 Year of experience in design as well as verification using verilog. Actually we are design IP Core and design verification environment in verilog to verify working of IP Core. I have design many test benches but i dont know about methods(architecture) that are used by MNC.  What is the generic method for define clock and reset in test bench(Sync & Asyn Design)?  I just want to know what is basic architecture require to verify any IP Core. can i have your personal E-Mail ID?