Numonyx StrataFlash Embedded Memory (P30) Conversion Milestone Update

[Altera_Forum]

Hello there, 

 I'am using Cyclone III with active parallel configuration in my hardware. In the Cyclone III Handbook is specified that i have to use the Numonyx P30/P33 flash family for AP Configuration Scheme.   OK. My design works fine with the PC28F256P30T85 ( 1,8 V ) ( 85 ns accsess time )   Now, Numonyx has changed his production from a 130nm to a 65nm process.   My Problem:  --> The read timing goes up from 85ns to 100ns. --> Power up timing goes from 60us to 300us. --> Word programming changes from 40us typ./175us max. to 150us typ./546us max.   There is no information about this change in the Quartus handbook or Cyclone III handbook.   Works the AP Configuration Scheme with the new timings ??? I'am using Quartus 8.1   Thanks for help

[Altera_Forum]

Anybody else have any info on this topic. I tried to ask the Altera mysupport, but they just told me to refer to the data book and numonxy datasheets.  

 No matter how many times I ask, Mysupport rep refers me to read datasheets.   Based on the datasheets this should work since the Altera data book only lists 40Mhz as the required timing parameter. Although I have not actually heard from anybody that this was tested.

[Altera_Forum]

Howdy. 

 I have done some testing cyclone III + commodity flash 65 nm parts. I used a PC28F256P30TF with a 1.8V core and 2.5V VCCIO. The design is generic with a single 3C80F780 connected directly to the PC28F256P30TF chip. There were no issues with repeated programming in Quartus and power up testing to verify Cyclone 3's hard ip support for direct reconfig using commodity flash. I didn't test the multiple image reconfig feature because I'm not there yet in the design.

[Altera_Forum]

Hi, 

 i have finished my design, and testing the PC28F256P30TF (BGA Package) in "Active Parallel Configuration" mode too. I use in my design 1.8V core and 1.8V VCCIO with a Cyclone III (EP3C16F484C7). There are no problems with the Quartus II Programmer or the Nios II Flash Programmer. But beware ! The new Flash timing is only supported in Quartus 9.0 and later versions. If you programm the Flash with Quartus 8.1 it will cause a verify error. My Altera FAE told me that the Flash timing is controlled by the Altera "Parallel Flash Loader" (Factory default PFL image). The PFL supports the new Flash timing at Quartus II 9.0 and later.