the "latch" problem

[Altera_Forum]

hello. 

there are some warnings occured during compilation.i do not know how to deal with the warning. Warning: Latch "calCD" has unsafe behavior  Warning: Ports D and ENA on the latch are fed by the same signal CurloopCal[1].   here is the code: always @ (posedge clk125M_i or posedge AsyRst_i)  begin  if(AsyRst_i)  begin  CurloopCal <=0;  end  else if(TimeEn_i)  begin  if(CurloopCal ==0)  begin  if(CureadFin_i)  begin  CurloopCal <=1;  end  else  begin  CurloopCal <=0;  end  end  else  begin  if(CurloopCal <6)  begin  CurloopCal <= CurloopCal+1;  end  else if(CurloopCal ==6)  begin  CurloopCal <=0;  end  else  begin  CurloopCal <=0;  end  end  end  else  begin  CurloopCal <=0;  end  end    always @(CurloopCal)  begin  case (CurloopCal)  4'd0:begin  calCP =0;  calCI =0;  calCD =0;  end  4'd1:begin  Cerr0 = Curexp - Curfbk;  end  4'd2:begin  delce = Cerr0-Cerr1;  end  4'd3:begin  sumce <= sumce+Cerr0;  Cerr1 <= Cerr0;  calCP =1;  calCI =1;  calCD =1;  end  4'd4:begin  RsutCPI = (RsutCP>>4)+(RsutCI>>4);  end  4'd5:begin  RsutCPID0 = RsutCPI+(RsutCD>>4);  end  default:begin end  endcase  end   thank you!!

[Altera_Forum]

substitute your instruction: 

 default:begin end  with  default: begin RsutCPID0<=1'bx; Add all the signals that are defined in the procedural block end  In the sensitivity list : always @(CurloopCal)  add the signals that are on the right side of the assignments such as: Cerr0 always @(CurloopCal,Cerr0)    This won't solve all the problems. As example you write: sumce <= sumce+Cerr0; That can waork only if a register holds the sumce value and the procedural block is sychronized with the clock.   I suggest to read a book on Verilog for synthesis.

[Altera_Forum]

Hello, 

I suggest you use V2K style (atleast) and use always @(*) for combinatorial logic blocks. That would resolve your sensitivity list issues. With SystemVerilog you are better off using always_comb. See:  http://www.slideshare.net/fpgacentral/upgrading-to-system-verilog-for-fpga-designs-srinivasan-venkataramanan-cvc  for the slides I presented at FPGACamp in Bangalore on SystemVerilog for FPGA designs.  HTH Srini www.cvcblr.com/blog