Same logic high ,but different voltage

[Altera_Forum]

Hi,guys. 

So why different pins have different voltage, while they are all logic high. (In my experiment,one is 1.14V, the other is 3.3V) Appreciate for any reply

[Altera_Forum]

Hi John  

AFAIK it can be one of the following cases: - pins located on different fpga banks, configured with different voltage standards - you have a problem in your design and 1.14V pin is driving a line which is an output from another device/pin; if this device is driving a logic low, then voltage will settle to a middle level; clearly this is not good for both the devices.  Regards Cris

[Altera_Forum]

Unfortunately, almost any necessary information is missing from your question: VCCIO, I/O standard, used device, connected load. You don't even tell if 1.14V is within specified Voh range for the respective IO standard.

[Altera_Forum]

Sorry for ambiguous statement. 

Cyclone II 2C35F672C6, VCC IO 5V, Default IO stardard 3.3LVTTL, 10 pF capacity load P.S. Even in the same dual in-line, pins voltage can be different when all of them are logic high. rely Cris: They are not ouput of other device or pin, just outputs

[Altera_Forum]

No Cyclone family supports higher VCCIO than 3.3V. Maximum in Cyclone II specified operation conditions is 3.6V. 1.14 V is clearly an invalid output voltage for 3.3V-LVTTL, so either the hardware or the configuration is wrong.

[Altera_Forum]

Thanks ,FVM. 

But PIN2 of the J15 is 5V, on the other hand pin1 is GND, which is read from reference manual. I also checked it by oscillograph. But not all the VCC io is 5V,some of them is 3.3V

[Altera_Forum]

Sounds like you are referring to a specific Dev Kit (e.g. C II Nios II board). Unfortunately you didn't yet tell. A 5V pin at a particular GPIO isn't directly connected to the FPGA, these Dev.Kits have additional circuitry between connector pins and FPGA, and also additional devices connected to some of the pins. In this case, the reported "1.14V" is meaningless without telling the exact DevKit and connector pin locations.

[Altera_Forum]

I got that. It is not FPGA which supports 5V in cyclone family. 

It is a Nios II development board cycloneII EP2C35 device. The pin is 12th of J15. Any solutions?

[Altera_Forum]

Did you notice, that the said pin (signal proto5_IO37) is also connected to the CF socket? Busswitch U22 is connected between the GPIO connector (proto5_IO37) and the FPGA (proto_IO37). If the problem persists, you should measure both sides of U22.

[Altera_Forum]

Yes, I noticed that. The said pin(proto5_IO37) is connected not only to U22, but also U30, which means that one pin connects to two busswitch devices. 

But could I measure both sides of them, 'cause I don't find any test point to check about. Another weird thing is the said pin ,which is proto5_IO37 ,is proto2_IO37 on refernce manual.

[Altera_Forum]

You should be able to measure TSSOP pins without testpoints.

[Altera_Forum]

Maybe I have to changed to some other pins. The test result look weird,too. 

But, anyway, thanks for all your patience and kind. John