Question about clock + PLL

[Altera_Forum]

Hi, probably that is going to be a very noob question but... 

 I am using PLL on a Clyclone II, and i was clocking some blocks directly from my 50Mhz oscilator input and some other blocks from a 100Mhz PLL output that have as an input my oscilator. That was generating me a Critical Warning on Classic Time Analyzer becouse of some path problems. But when i changed and instead of sending my input clocks directly to the blocks i used the second output of the PLL with no multiplication, the warning was gone. Why thats happened if PLL is suposed to lock the output phase with the input?   Let me know if i was not enough clear.   Thank you!

[Altera_Forum]

Depends on the nature of the said warnings. The 100 MHz clock may be simply too fast for your design.

[Altera_Forum]

The warning was: Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. 

 But if 100Mhz is too fast for my design, why the critical warning and all other time warning just disapeared after i used the 1:1 output of PLL instead of using the input directly? Actualy it does not generate a warning even at 200Mhz.... (the 200Mhz is just used for sample purposes on a UART receiver). And that 200Mhz had the same use of the 100Mhz one... And the paths that were generating the warning were the 50Mhz ones and not 100Mhz...   I think i was kind confusing at my description.. was that understandable?   Thank you!

[Altera_Forum]

PLLs inside FPGAs are normally happy if they have their clock input dedicated to them only i.e. not driving anything else. That is what you did when you changed your design.

[Altera_Forum]

Thank you very much, i will take that on consideration on my next designs. Very usefull information!

[Altera_Forum]

I didn't understand your above description at first look. ALthough the PLL output is locked to the input clock, there's additional delay skew between in- and output clock.

[Altera_Forum]

It was my impression that the general course of action was to use a 1/1 divider for one of the pll outputs if you want to use the base clock frequency. At the very basic level, there is no guarantee that the pll is exactly synchronous in phase with the input clock. This might not be a problem if you are clocking completely independent modules that have no interaction (and therefore you might be safe in ignoring the warnings), but as kaz pointed out, there are other factors to consider, like the input requirements of the pll.

[Altera_Forum]

This is probably (OP didn't provide too much details) an issue of hold timing violations due to transfers between the original clock and the PLL output one.