Why is there one cycle delay for a simple counter?

[Altera_Forum]

The code is as the following: 

===================== `timescale 1ns/1ps  module counter(clk, rst_n, cnt);  input clk; input rst_n; output[3:0] cnt;  reg[3:0] cnt;  always @(posedge clk) begin  if(!rst_n) begin cnt<=4'b0; end  else if(cnt<4'd9) begin cnt<=cnt+4'b1; end  else begin cnt<=4'b0; end  end  endmodule

[Altera_Forum]

The problematic waveform is as the following: 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=2839   Whether the reset is asserted or deasserted, there is one cycle delay.

[Altera_Forum]

The tools setting are: 

 Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version Device EP1C6Q240C8 Timing Models Final

[Altera_Forum]

I can't reproduce your simulation waveform. It look like it's belonging to a different design. You may want to post a Quartus archive that contains the project with the simulation waveform.

[Altera_Forum]

i can't reproduce your problematic waveform too.have you try to use another simulator?like modelsim.

[Altera_Forum]

The answer can perhaps be as simple as: the design doesn't work at 100 MHz. The fact that the count reaches 5 was the hint for me. 

I usually simulate at lower frequencies (40 MHz or so) just to make life easy on drawing and interpreting the waveforms, otherwise you have to pay attention on the Tsu and Tco times involved.

[Altera_Forum]

Yes, you're right. The counter can work at higher clock speeds than 100 MHz, but the rst_n setup time is too short. The 5 ns is exactly at the edge, it happened, that the timing of my simulation waveform was slightly different.

[Altera_Forum]

https://www.alteraforum.com/forum/attachment.php?attachmentid=2850  

 The archive is attached.   One strange thing is that: I once do the same thing on Quartus 8.1 web edition. If rst_n is low, there is one cycle delay. If rst_n is high, there is NO one cycle delay. It seems that different version has different compiling policy.  Someone told me that I can set constraints to make it work normal. I am a starter on FPGA. Can anyone help to show how to set up constraints? Many thanks.

[Altera_Forum]

BTY, in simulation, I use slow model. If I use fast model, there is no such problem.

[Altera_Forum]

I compiled your design.  

If you look at the TimeQuest report we find: Setup : clk 7.041 0.000 Hold: clk 1.058 0.000 In your .vwf you only have a 5.000 ns setup time for rst_n to clk rising. Hence the design may fail, and the simulator does show so. I shifted the rst_n signal 2.5 ns to the left, creating 7.5 ns setup time, and the simulator runs fine. The clock to output is 7.731 ns which makes reading the simulation output a bit difficult.v See the attached image. (I usually use slower clocks even to simulate higher speed designs, just to make setting up and reading signals easier)   You can obtain better setup, hold and clock to output times, but the add proper constraints to your .sdc file.

[Altera_Forum]

Many thanks yo josyb. 

 I am a starter and do not know how to add proper constraints. Can you help to give examples or point out some documents so that I can read? Thanks.