ModelSim halts with 'ERROR: cpu_test_bench/M_en is 'x' '

Altera_Forum · ‎09-07-2010

Hi,

I created a SOPC system, according to an Altera tutorial. The system consists of a Nios-II and several peripherals. After system creation, I fired up EDS (Eclipse), compiled a BSP and 'hello world' project, and started ModelSim from within Eclipse/EDS.

In ModelSim, after just a bit of simulation, I hit a stop condition in the cpu test bench:

always @(posedge clk)
    begin
      if (reset_n)
          if (^(M_en) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_test_bench/M_en is 'x'\n", $time);
              $stop;
            end
    end

I browsed through the source code, the signal M_en is driven by an intricate net of signals with mysterious names such as 'n001O1', which does not make the Verilog code very readable. But perhaps that is the intention, since the compiled verilog (cpu.vo) file is human readable, but the incoming source (cpu.v) is garbled.

I also browsed the forum for this problem, could find somebody else reporting it but saw no solution. Is this perhaps a bug that is fixed with a later Quartus/ModelSim/EDS release ?

Thanks, Roland.

PS: using Quartus II V9.1SP2

Altera_Forum · ‎09-08-2010

Problem found and fixed. It turned out to be a missing memory initialization file that defined flash memory contents (containing the 'hello world' project). Still it is puzzling to me why the Eclipse IDE does not create these .dat files automatically as part of the build process. I had to go to a command prompt and type 'make mem_init_install' to accomplish this. Application Note AN351 was helpful for me to find this information.

I root caused the problem by observing the wave window, which showed that the system accessed external flash memory several times before crashing. The value read was undefined. Ultimately this led to the 'M_en stop' condition as described in my previous post.

So, although the problem is solved, a couple of questions:

1. Is there an automated way to generate these .dat files from within the Eclipse IDE ?

2. Is there any documentation on the cpu test bench. For instance, what does this 'M_en' signal represent ? Master enable ? Memory enable ?

3. Why are the majority of nets in cpu.vo named like 'n001O1' instead of human readable names, and why are they lumped together into one big structural description that is hard to debug. Is it Altera's intention to obfuscate the SOPC generated code ?

4. If so, why is cpu.v then unreadable (contains binary data) but the resulting cpu.vo is human readable ?

Thanks, Roland.