Cyclone4 NIOS can only run at 60M?

[Altera_Forum]

hi every one; 

first using niosii , with the demo board"civgx_trans_starter_board" which is EP4CGX15BF14;  using the example"bts_general" offered by the kit, this example contains"TSE/SSRAM/FLASH...."  after complie the project found the fmax of the system only 62M; the worst falling path is the "sgdma to flash"；  my purpose is using the GE port to control the other logic of FPGA(write/read registers), and the required efficiency should be"2~3 hundreds command per seconds";   sound very difficult?

[Altera_Forum]

You can add Avalon MM pipeline bridges to increase the fmax. You could put one between the SGDMA masters and the RAM, as an example. Another one before the JTAG debug module in the CPU usually helps too.

[Altera_Forum]

--- Quote Start ---  You can add Avalon MM pipeline bridges to increase the fmax. You could put one between the SGDMA masters and the RAM, as an example. Another one before the JTAG debug module in the CPU usually helps too.  --- Quote End ---    thanks verymuch； I'll have a try，but i think this could not increase the fmax verymuch, and is there any reference tells about niosii fmax on cyclone4? haven't found any;  another questions is：when I generate the core, it said"time limited, no rbf would be generated" but how could i know which core is"limited"?

[Altera_Forum]

You're wrong, pipelining does increase fmax a lot, when you put them at the right place. I don't know if there is any documentation about the fmax of a Nios setup, because it depends a lot on the configuration. 

On Cyclone III it is very easy to reach 100MHz, and with some care 120MHz shouldn't be a problem. I never tried to get over that. Have a look at the SOPC builder log during generation, I think it says which core(s) don't have a license.