Arria II GX DDR2 issues with .QSF file

[Altera_Forum]

I have been banging my head against a wall for the last day and I hope I can get a solution to this. 

 Challenge: Generated a HPCII DDR2 controller using the Megawizard, not an issue. The top level of the project with the controller is synthesizing fine including the controller. The problem comes with the DQSN signal in the qsf file. Here are the assignment statements in the qsf file:  # set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQS set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MEM_DQS set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQSN set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MEM_DQSN set_location_assignment PIN_AM25 -to MEM_DQS[0] set_location_assignment PIN_AM26 -to MEM_DQSN[0] set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to MEM_DQS set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to MEM_DQSN set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQS[0]#   These statements are essentially a copy from the golden qsf file from the ARRIA II GX devbrd kit. During fitting I get this message:  Error: Can't place node "MEM_DQSN[0]" -- node is a differential I/O node  I have tried multiple changes to these statements and nothing is working.  Ideas?  pinscore

[Altera_Forum]

IO Standard for DQS/DQSn should be Differential SSTL-18 Class I. When you enter pin AM25, edit the differential column and change mem_dqs[0](n) to mem_dqsn [0] 

 I spent some time on this and finally got the example_top to work. The documentation and material that comes with the kit is very hard to follow and not as complete or clear as it could be.

[Altera_Forum]

So you are saying change: 

 set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQSN  to  set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQSN[0]  ? 

[Altera_Forum]

Tried the change and it gave me the same error...

[Altera_Forum]

The IO standard should be "differential sstl-18 class i". If you do not specify that, Quartus will think you are doing single-ended DQS signals. In the pin planner, choose the Differential SSTL-18 Class I from the drop down list. You should a line like this: 

 set_instance_assignment -name io_standard "differential 1.8-v hstl class i" -to mem_dqs[0]  (adjust for pin name if it is not mem_dqs)

[Altera_Forum]

I did the change and wow...now I am getting some major bank conflict errors, but I got past the original. 

 The pins in conflict are set for 2.5v default. I am assuming that if I change them to either the 1.8V or 1.8V HSTL that would work?

[Altera_Forum]

In the pin planner, you can highlight the IO banks. Anything that shares the bank with the DDR2 should probably be 1.8V. Look at the dev board schematic sheet 26 to find out which bank has which voltage and correlate that with the voltage values on page 18 (and probably others)