Error (10170): Verilog HDL syntax error

Altera_Forum · ‎09-21-2010

Having trouble with my Verilog HDL file. Fairly new at this so hopefully this is simple.

Unable to compile because of this error:

Error (10170): Verilog HDL syntax error at four_bit_addertb.v(11) near text "["; expecting ")"

Line 11 is:

four_bit_adder t1(.Cin(N_s), .A(A_s), .B(B_s), .A( C_s), .B( D_s), .A( E_s), .B( F_s), .A( G_s), .B( H_s), .S(S_s), .S(SS_s), .S(SSS_s), .S(SSSS_s), .Cout(O_s));

Now if I take out the [] brackets and just have A0, B0, A1...etc

It compiles but does not simulate...I imagine since A0 doesn't refer to anything. The schematic (.bdf) file has the inputs labeled as A[0], B[0], A[1], B[1], and so on. How is this handled? I put quotes around it...no luck. The class I'm in has them labeled that way.

Altera_Forum · ‎09-21-2010

You should show a Verilog port definition of four_bit_adder for clarity. However, if the bit identifier A[0] appears in the module's port list, it's not a port name. The port is unnamed in this case and you can't use named notation in instantiation of the module. Use positional instantiation instead, or change the port definition of the module to use simple identifiers.