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Hi all.
I was able to do a NIOS setup using a SDRAM, SRAM, VGA Controller, and more. It's working fine in my DE2 board, and I was able too, of download all the code in the ECPS succesufully. So now my DE2 board execute my config when I power up it. The questions are: If I want to design my own board using this config, How do I know which EPCS memory choose ?? (How many bits I need in it). Is the sum of the all flash files generated? Which is the NIOS program memory ? Is ti using the SDRAM ? if I choose this used as exception vector ??. So I don't know ...how many bytes of "C" code I can download to this "new board". Sorry, seems to be very begginer questions, of an advanced problem. Cheers. Alberto.Link Copied
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Please, anyone could help me with this...
It will be really apreciated. Thank you. Alberto.- Mark as New
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The EPCS needs to be, at least, be big enough to hold the FPGA configuration and the NIOS system image.
The FPGA configuration's size is fixed for a FPGA model, unless you use compression. In this case, it will vary with your design. The size of the NIOS image will depend on what you put in it. Regarding program memory, it's your SOPC, you should know what's being used.- Mark as New
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--- Quote Start --- The EPCS needs to be, at least, be big enough to hold the FPGA configuration and the NIOS system image. The FPGA configuration's size is fixed for a FPGA model, unless you use compression. In this case, it will vary with your design. The size of the NIOS image will depend on what you put in it. Regarding program memory, it's your SOPC, you should know what's being used. --- Quote End --- Thank you rbugalho. But that is why I want to know, first I've a .flash file for my FPGA design, then I've two .flash files more (I commented it above). The point is, for that FPGA configuration, and for that files generated by the "flash programmer", should I choose a EPCS device with enough bytes which that .flash files sum ? Remember, I've all that code running on a DE2 board, but this board have a EPCS64, too big and too expensive, if my project fits in a EPCS16 or less, I could save a lot of money for my design, (and this is my fisrt one using an FPGA) I'm self study guy, believe me, I'm able to do all this working fine, but I'm still not able to know... which is the size of my project to fit in the EPCS, all I've is the files that the flash programmer has generated. Maybe the question is trivial for you, but not for me. Thanks again ! Alberto.
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Alberto,
The .flash files are really just SREC (SRecords), so their size is not what matters. It's the binary content they contain that really matters. Fortunately, there's an easy solution. binutils, included with the Nios II toolchain, has a utility called "size" which can determine the binary size of an SREC. Just type...nios2-elf-size <.flash file>
...from a Nios II Command Shell, and you'll know the actual amount of memory these files consume when programmed. Adding these together will give you the total size. Cheers, --slacker
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Hi,
first of all I would recommend you too read this table. Here you can see the which device is minimal needed for your FPGA: http://www.altera.com/products/devices/serialcfg/overview/scg-overview.html- Mark as New
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--- Quote Start --- Alberto, The .flash files are really just SREC (SRecords), so their size is not what matters. It's the binary content they contain that really matters. Fortunately, there's an easy solution. binutils, included with the Nios II toolchain, has a utility called "size" which can determine the binary size of an SREC. Just type...
nios2-elf-size <.flash file>
...from a Nios II Command Shell, and you'll know the actual amount of memory these files consume when programmed. Adding these together will give you the total size. Cheers, --slacker --- Quote End --- Thank you so much slacker. That's exactly what I need to continue with the design !!!!! Cheers. Alberto.
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