Choice und Design of CPLD

[Altera_Forum]

Hi Folks, 

 I am a beginner in matters of CPLD/FPGA Design and hope not to bother you too much with my rookie questions. But I would be very glad if you could help me out and please excuse English mistakes (since it's not my mother tongue).  Over the last couple of weeks I have developed a Schematic File in Quartus II, which works the way I wish in functional analysis. This week I wanted to choose and order a Device to implement the design and test it with a scope-  In the last days two questions have come up, which I would like to ask you. I have searched this forum but haven't found the answer to my question.  1) So far I have analysed the size of my design and the Quartus Fitter and agrees on my choice of a MAX II CPLD. So far so good, as I have read in this forum as well as in the Quartus II Handbook it is strongly advised to run Timing Analysis, which I tried to do in the last days (Time Quest Analyzer and Classic Timing Analysis).  In my design there is one and only clock, which I want to run with a certain frequency (40 MHz). I know this frequency as well the frequency of changes of the inputs.  Timing Analysis asks also e.g. for Setup and Hold times of logic elements and Altera/Quartus suggests to give constraints for every path.   My actual question is: How I can find out the constraints in my design which are not directly related to the maximum clock frequency? Right now, I don't know which constraints a I have since I always thought, that my design works well as long as the maximum clock frequency is alright with the design.   2) A probably very simple question:   I want to use a SR-Flipflop or rather a storage element in my device, which gives out Zero as long as the input is Zero. If the input of the element changes to One, this should be stored until the element is manually reset. The problem with the SRFF is, that it has two inputs and it doesn't work, when the inputs are the same.  At present I am using a Latch/DFF and the D and ENA/Clock input get the same signal and I reset the element with the CLRN input, which works fine in functional analysis.  Is this in your opinion an acceptable implementation of the desired functionality?  Thanking you in advance for any help.  Greeting!

[Altera_Forum]

--- Quote Start ---  Hi Folks,  I am a beginner in matters of CPLD/FPGA Design and hope not to bother you too much with my rookie questions. But I would be very glad if you could help me out and please excuse English mistakes (since it's not my mother tongue).  Over the last couple of weeks I have developed a Schematic File in Quartus II, which works the way I wish in functional analysis. This week I wanted to choose and order a Device to implement the design and test it with a scope-  In the last days two questions have come up, which I would like to ask you. I have searched this forum but haven't found the answer to my question.  1) So far I have analysed the size of my design and the Quartus Fitter and agrees on my choice of a MAX II CPLD. So far so good, as I have read in this forum as well as in the Quartus II Handbook it is strongly advised to run Timing Analysis, which I tried to do in the last days (Time Quest Analyzer and Classic Timing Analysis).  In my design there is one and only clock, which I want to run with a certain frequency (40 MHz). I know this frequency as well the frequency of changes of the inputs.  Timing Analysis asks also e.g. for Setup and Hold times of logic elements and Altera/Quartus suggests to give constraints for every path.   My actual question is: How I can find out the constraints in my design which are not directly related to the maximum clock frequency? Right now, I don't know which constraints a I have since I always thought, that my design works well as long as the maximum clock frequency is alright with the design.   2) A probably very simple question:   I want to use a SR-Flipflop or rather a storage element in my device, which gives out Zero as long as the input is Zero. If the input of the element changes to One, this should be stored until the element is manually reset. The problem with the SRFF is, that it has two inputs and it doesn't work, when the inputs are the same.  At present I am using a Latch/DFF and the D and ENA/Clock input get the same signal and I reset the element with the CLRN input, which works fine in functional analysis.  Is this in your opinion an acceptable implementation of the desired functionality?  Thanking you in advance for any help.  Greeting!  --- Quote End ---    Hi,  in your post you mentioned that you have a clock in your design available. That's good,  because you can develop a synchronous design. Have a look to the small project I have attached. Is that the function you would like to implement ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  in your post you mentioned that you have a clock in your design available. That's good,  because you can develop a synchronous design. Have a look to the small project I have attached. Is that the function you would like to implement ?  Kind regards  GPK  --- Quote End ---    Hi,  I forgot to answer your first question. The input and output constraints depend on the circuit which drives the FPGA ( when are the data stable in relation to the clock) and the timing requirements of the circuit which is driven by the FPGA ( when must be the output data of the FPGA stable in relation of the clock of the receiving circuit).  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  in your post you mentioned that you have a clock in your design available. That's good,  because you can develop a synchronous design. Have a look to the small project I have attached. Is that the function you would like to implement ?  Kind regards  GPK  --- Quote End ---     Awesome, thanks for your response! At first I wanted to have these storage elements working asynchronous, but I guess I'll focus on having everything working synchronous, which will probably save time for debugging. But is it okay and synchronous design then, to lead back the output of the Flipflop to the Enable-Input of the FF? I negated the reset input, but otherwise it's just what I needed. Thanks!   --- Quote Start ---  Hi,  I forgot to answer your first question. The input and output constraints depend on the circuit which drives the FPGA ( when are the data stable in relation to the clock) and the timing requirements of the circuit which is driven by the FPGA ( when must be the output data of the FPGA stable in relation of the clock of the receiving circuit).  Kind regards  GPK  --- Quote End ---     I still don't know whether I understood it correctly: So I pass the Timing Analysis Tool the constraints of the signals which enter the CPLD-Design (Input ports) and which leave the CPLD (Outputs) to the PCB and I make sure that these signals work fine with the Setup & Hold-Times of the CPLD. Sorry, if my assumptions seem stupid. I am trying really hard to comprehend what goes on within and outside the CPLD. Greetings!

[Altera_Forum]

--- Quote Start ---  Awesome, thanks for your response! At first I wanted to have these storage elements working asynchronous, but I guess I'll focus on having everything working synchronous. But is it okay then, to lead back the output of the Flipflop to the Enable-Input of the FF? I negated the reset input, but otherwise it's just what I needed. Thanks!  --- Quote End ---    Hi,  the feedback to the enable should be ok, because Quartus will handle the timing.  Kind regards  GPK