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Hello,
I am looking for some advice - hopefully i have made a schoolboy error. I have a problem with an output from a cyclone III starter kit. I have written a very basic block of code in VHDL to send the clock from the board directly to one of the outputs:library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY hsmc_test IS
PORT ( input : IN STD_LOGIC;
hsmc : OUT STD_LOGIC);
END hsmc_test;
ARCHITECTURE behav OF hsmc_test IS
BEGIN
hsmc <= input;
END behav;
In the pin planner i have tried several settings for the IO standard inlcuding: 3.0V LVCMOS, 3.0V LV TTL etc. The problem is that the output is only being driven to about 700mV peak to peak. I am using Quartus II version 8.0. I origionally had a more complicated VHDL function which was working in simulation but not in hardware. The external hardware i am trying to drive requires the clock from the FPGA to have a minimum 2.5V for logic high, therefore i assume that this is the reason i had a problem. I would be grateful for any assistance. Thanks in advance. Regards Ade
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Do you have a ground connection between the starter kit and the external hardware?
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