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Low voltage for output from Cyclone III starter kit

Altera_Forum
Honored Contributor II
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Hello, 

 

I am looking for some advice - hopefully i have made a schoolboy error. 

 

I have a problem with an output from a cyclone III starter kit. 

 

I have written a very basic block of code in VHDL to send the clock from the board directly to one of the outputs: 

 

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY hsmc_test IS PORT ( input : IN STD_LOGIC; hsmc : OUT STD_LOGIC); END hsmc_test; ARCHITECTURE behav OF hsmc_test IS BEGIN hsmc <= input; END behav; 

 

In the pin planner i have tried several settings for the IO standard inlcuding: 

3.0V LVCMOS, 3.0V LV TTL etc. 

 

The problem is that the output is only being driven to about 700mV peak to peak. 

 

I am using Quartus II version 8.0. 

 

I origionally had a more complicated VHDL function which was working in simulation but not in hardware. 

 

The external hardware i am trying to drive requires the clock from the FPGA to have a minimum 2.5V for logic high, therefore i assume that this is the reason i had a problem. 

 

I would be grateful for any assistance. Thanks in advance.  

 

Regards 

 

Ade
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Altera_Forum
Honored Contributor II
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All I/O banks of the Cyclone III starter board are powered by 2.5 V. So you should always get a 2.5 V square wave using a single ended I/O standard. 2.5V would the be the correct one, but there's no functional difference if you assign e.g. 3.0V LVCMOS. 

 

I wonder if it can be a problem of not correctly probing the output signals at the HSMC connector?
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hello, 

 

I am looking for some advice - hopefully i have made a schoolboy error. 

 

I have a problem with an output from a cyclone III starter kit. 

 

I have written a very basic block of code in VHDL to send the clock from the board directly to one of the outputs: 

 

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY hsmc_test IS PORT ( input : IN STD_LOGIC; hsmc : OUT STD_LOGIC); END hsmc_test; ARCHITECTURE behav OF hsmc_test IS BEGIN hsmc <= input; END behav; 

 

In the pin planner i have tried several settings for the IO standard inlcuding: 

3.0V LVCMOS, 3.0V LV TTL etc. 

 

The problem is that the output is only being driven to about 700mV peak to peak. 

 

I am using Quartus II version 8.0. 

 

I origionally had a more complicated VHDL function which was working in simulation but not in hardware. 

 

The external hardware i am trying to drive requires the clock from the FPGA to have a minimum 2.5V for logic high, therefore i assume that this is the reason i had a problem. 

 

I would be grateful for any assistance. Thanks in advance.  

 

Regards 

 

Ade 

--- Quote End ---  

 

 

With the 700mV comment, what power supply are you useing, how are the grounds connected? With some development board they are powered via a bridge rectifer that can cause an issue if the 0V of the supply is referenced to GND. What waveform do you see and could you post it somewhere? Also what is the frequency you are looking at, sampleing frequency of the scope and have you got it set to 1M instead of 50 ohms? 

 

Thanks
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Altera_Forum
Honored Contributor II
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Hi FvM and UK Fixer, 

 

Thanks for the input - i suspected a possible grounding issue between the cyclone starter kit and ext hardware so i disconnected everything and measured the output signal directly from HSMC connector on the starter kit itself. 

 

The situation is still the same 

 

I have an image of the waveform from my scope - i have no means of oploading or attatching it. I would gladly send it via email or messenger if you would welcome me to do so.  

 

Its shows an almost sinusoidal wave with a frequency of 50Mhz (this is the frequency of the onboard oscillator so is correct), and p-p Voltage of 750mV. 

 

This seems strange in itself because for the afore mentioned code, should i not expect a squarewave function at the output??? 

 

Regarding the scope - i have default parameters set, i dont think i have any option to change the sampling frequency (i beleive it is automtically set) and the impedance of the probe inputs is 1Mohm not 50ohms. 

Should this have an effect? 

 

Many thanks.  

 

Ade
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Altera_Forum
Honored Contributor II
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The FPGA output waveform is surely not a sine. So if you see a sine, there's apparently either a lowpass filter in your oscilloscope or the signal isn't transmitted with full bandwidth to the oscilloscope. In this case, the shown amplitude is meaningless.

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Altera_Forum
Honored Contributor II
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Maybe i am confusing the issues by saying i see a sine - its more like a smoothed traingluar wave. 

 

Would you object to me sending you the image? I am sure you could tell me whether it is what i should expect pretty quickly. 

 

Many thanks.
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Altera_Forum
Honored Contributor II
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After some further investigation it would appear i am getting alot of attenuation from my scope at higher frequencies. 

 

When i run the clock OP in the low KHz i get a perfect square wave with 2.6v p-p. 

 

Thanks for all your help. 

 

Ade
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