Arria II GX + DIMM = no more than 12 HSTL/SSTL output or bi-directional pins are allo

[Altera_Forum]

I'm trying to get my EP2AGX45 (572 package) Arria II GX to interface with a DIMM. I've run into an apparent limitation of 12 SSTL signals per I/O bank. It seems i will have to move up to the top device EP2AGX260 (1152 package) to get more I/O banks. It seems all other devices inbetween only have larger banks but not more banks. 

 Is this SSTL/bidir limitation due to the number of pins in the banks? Would a larger package (say 780 pins) allow more SSTL-18 signals? If so, how many?  This behavior seems largely undocumented.  =============================================  Error: Total number of HSTL/SSTL output or bi-directional pins in I/O module RIO6 is 13 -- no more than 12 HSTL/SSTL output or bi-directional pins are allowed in a I/O module Error: Total number of HSTL/SSTL output or bi-directional pins in I/O module RIO6 is 13 -- no more than 12 HSTL/SSTL output or bi-directional pins are allowed in a I/O module Error: Can't fit design in device Error: Quartus II Fitter was unsuccessful. 3 errors, 5 warnings  Error: Peak virtual memory: 234 megabytes  Error: Processing ended: Tue Oct 05 00:24:03 2010  Error: Elapsed time: 00:00:30  Error: Total CPU time (on all processors): 00:00:28 Error: Quartus II Full Compilation was unsuccessful. 5 errors, 186 warnings

[Altera_Forum]

I have the same issue in my design which targets an EP2AGX190FF35C5 (1152 pins). In my case, I have two DDR2 interfaces (16-bit) on the same edge of the chip. 

 Based on the external memory interface documentation, I could put up to six DDR2 interfaces (16-bit) on each edge of the FPGA...  With the error we have, no-one will achieve to fit six DDR2 interfaces on the same edge, Quartus will say that there are too many output/bidir pins in the same I/O module... Something's wrong here, either the doc has boosted the numbers, or there is a way to fix this error in Quartus...  Martin

[Altera_Forum]

The problem is usually brought up by not correctly defining the output enable groups for the bidirectional memory data path. If you follow the suggested design flow for the DDR controller, tcl files containing the respective settings are automatically imported to the design assignments. The point is, that all bidrectional data and dqs pins of a DDR RAM are set as input or output simultaneously. Thus, the limitation for maximum allowed number of output or bidirectional pins in a bank does not apply. Quartus is using the attribute output enable group to mark those pins, that are driving simultaneoulsy.

[Altera_Forum]

FYI: I ended up fitting my (64-bit) SO-DIMM in a 780-pin EP2AGX45DF29C6. I span the interface over banks 5A, 6A, 7A and 8A.

[Altera_Forum]

As far as I see, a 64-Bit DIMM can be operated from 3 IO banks in the 572 and 780-pin package. The limiting factor is the number of availiable DQS groups. The said "limitation of 12 SSTL signals per I/O bank" is caused by incomplete pin assignments.

[Altera_Forum]

I ran into the same issue. This is documented in http://www.altera.com/literature/dp/arria-ii-gx/pcg-01007.pdf . Look at note 12 on page 7. There is also a correction/clarification for that note somewhere else, but I forget where. 

 FvM, are you saying that I can use diff DQS and bidirectional DQ pins with SSTL standard and still be able to go beyond the 12-pin limit?

[Altera_Forum]

--- Quote Start ---  As far as I see, a 64-Bit DIMM can be operated from 3 IO banks in the 572 and 780-pin package. The limiting factor is the number of availiable DQS groups. The said "limitation of 12 SSTL signals per I/O bank" is caused by incomplete pin assignments.  --- Quote End ---    I was not able to fit the DIMM interface in the 572-pin Arria II package, even when using four I/O banks. The 572-pin EP2AGX45 has 4 DQ groups on the top side and 4 DQ groups on the bottom side so the number of DQ groups should not be the limitation.  All I/Os were configured correctly via the QII-generated TCL scripts. When moving up to the 780pin package the design would fit in the same four I/O banks. I think the number of available SSTL-capable pins in each I/O bank is limited due to the physical 572-pin package. I'm sticking with the 780-pin package unless someone can prove that a DIMM somehow can be hooked up to the 572-package (I have not found a single example of this anywhere). In my case the price difference is about $100 so not too critical for my end product.

[Altera_Forum]

I didn't try with differential DQS. To see, what's the problem with 572-pin Arria II, I would have to implement a test design. I was originally referring to the reported "12 SSTL signal limitation" which is known as a problem of missing OE-group assignments. It may be the case, that Arria II has additional restrictions, that don't allow to implement a 64-Bit RAM interface with 572-pin package. If so, it would be a chip design or Quartus flaw.  

 I implemented however a DIMM interface with only two 1.8V banks of 1120-pin Arria, which should give an almost comparable number of available memory pins.