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Program storage

Altera_Forum
Honored Contributor II
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I am designing a system that will have time-critical and non-time-critical instruction. I want to store all the time-critical instruction and data in on-chip RAM and the other in external SDRAM. How would accomplish this when I develop the program.  

 

At first, tightly couple memory sound like a solution but it only applicable to on-chip RAM not external memory. Is there a way I can specify sections of code as going to SDRAM or on-chip. 

 

Thanks
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Altera_Forum
Honored Contributor II
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if you are using Nios IDE, do the following: 

 

Window > open perspective > Nios C\C++ 

 

In the left had side, right click on your project folder.  

 

then select System Library Properties 

 

you should see the selection boxes for all your code and memory allocation on the right hand side.  

 

All sections of your program can be moved to different memories 

 

.text, .rodata, .rwdata, heap, and stack can all me moved around.  

 

If you want to move certain functions to different sections in memory,  

 

you will need to either use pragmas or manipulate your memory map.  

 

I haven't done that in Nios, but the nios documentation does tell how I believe.  

 

First you need to develop your code and see if it exceeds your onboard memory size first. It seems to me that Altera did a good job on selecting the right ammount of on board ram for a given fpga. Meaning the Ram/logic ratios are good. 

 

You may not need to store any code in off chip ram.  

 

good luck.
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Altera_Forum
Honored Contributor II
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Spaugh, 

 

The Nios II application program is going to be too big for on-chip memory since I have used a lot of M9K blocks for a lot of the hw modules. 

 

I want to be able to put some C functions that will be doing critical time function on some allocated on chip memory. pragma seem to be a good way to separate such functions but I am not aware of any Nios docs that describe how to accomplish this with pragma. If you do, I will appreciate the ref.  

 

By the way, I am using Nios II SBT design flow. 

 

Thanks a lot
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Altera_Forum
Honored Contributor II
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ok, well you will definetly need to figure out how to move some functions to on board ram and some to off chip. 

 

I am going to be in the same boat shortly. I am starting to run out of on chip ram. I did a board spin because of this and put a ram on it just for this purpose. I will be trying to figure it out too.  

 

Have you done an OBJ dump yet? that will give you your memory map.  

 

I still don't know how to modify it though. 

 

I used to work for a company that was using TI DSP C55X and there we had several different levels of memory with different latencies. 

 

We were able to modify a linkmap command file and use pragmas in the C code to tell the linker which section to put each function in.  

 

There must be a way to modify some linker script in the Nios IDE.  

 

Problem is I am the only engineer doing board design, VHDL design and writing all the SW. I'm drowning! hopefully someone can help us with this cause I don't have time to blow trying to figure out something that should be in the Altera documentation. :(
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Altera_Forum
Honored Contributor II
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ok, i found something called the .section directive.  

 

this is a directive that you can put after a data or function declairation like a pragma that will direct the linker to put that piece of code or data into a particular section. 

 

If you search your project for a file called generated.x you will find your auto generated linker script. Within this file you can find the different sections that are hooked to your instruction and data ports of your nios.  

 

You need the instruction port of nios hook to any memory you want to run code from (obviously) and then you should be able to use the .section directive to guide the linker. I don't have an example but search around and I think you will find one.  

 

even easier might be to hook nios instruction and data busses to your off chip ram and tell tell the IDE to use that memory section for .text section. 

 

Then any functions you want to run faster, just set up a tightly coupled memory. There is documentation for that. 

 

good luck, let me know how it goes.
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Altera_Forum
Honored Contributor II
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The section directive, and a carefully written linker script will let you assign different code and data to different memory areas. 

You'll also need to consider how your code gets loaded. 

If you are loading from the elf program image file (as the jtag loader does, and I do from an external processor) then you want the elf program headers to load all the sections to their physical addresses. 

Some of the altera linker scripts (and their startup code) will append the initialised data for other sections onto the main code section, and have the startup code copy it into place! This doesn't work very well when your main code is 8k ands you have a 12k block of preinitialied data for a different data segment! Check with 'objdump -p' and by looking at the linkers .map output file. 

 

If you are looking at code/data segments you may want to consider: 

- using the 'small data segment' for things in tightly coupled memory. 

- putting the 'rodata' into a data area (not with thge code). 

- depending on your application, avoiding ALL of libc and not using the altera startup code (including the code that calls alt_main(). 

 

It is perfectly possible to do real things in a few kb of code.
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