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In using TimeQuest, I have come across the following warning:
"Warning: The launch and latch times for the relationship between source clock: V_AABCLK1 and destination clock: bpll|altpll_component|auto_generated|pll1|clk[0] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0." In this particular case, the source clock is 3.072MHz and the destination clock is 54MHz. In my design, I passed the corresponding data signal through a synchronizing chain in which I registered the signal first at 3.072MHz and then twice at 54MHz. I am seeing negative setup slack related to the crossover between the 3.072MHz register and the first 54MHz register. I have come across one other post with relation to this error and absolutely nothing in terms of the Altera documents. Any assistance in understanding what is creating this warning would be greatly appreciated.Link Copied
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Well, if you provide synchronizer chains and the clocks are not related, you can just break the path between them and not worry about it. As the clocks are note related, the analysis doesn't matter and isn't valid.
my 2cents Kevin- Mark as New
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I agree. Just declare a false path between the two clock domains, if you are sure that *all* the domain crosses are properly synchronized as you described.
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Reading various TimeQuest documents has led me to believe that, if domain crosses are properly synchronized, the analyzer will recognize this on its own, thus removing the need to false-path the initial cross from one domain to another. Am I incorrect in assuming this? Is it not better to multicycle the offending path to correct the launch/latch timing behavior?
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No those aren't recognized automatically by Timequest for setup and hold analysis, you must declare them as false paths.
The domain crosses are automatically recognized during the metastability analysis though.- Mark as New
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Thank you. This will save me a lot of time and headaches.
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