Arria II DDR2 clock assignment

[Altera_Forum]

Hello, 

 I am trying to use 2 x16 DDR2 chips and combine them as 1 x32 DDR2 using the HP DDR2 IP. I am using differential DQS and have one CK/CK# pair per chip.  In the emi_plan_pin document (version 2.0) page 2-16, it says that if I use diff DQS, I have to put the first clock pair in a pin with DIFFIO_RX or DIFFIN and the second clock in a pin with DIFF_OUT in the same single DQ group.  In the Arria II package I am using, each x8 group allows a max of 12 pins to be used. So, 8 DQ + 2 DQS is 10 pins leaving 2 pins for other assignments. Since I need 4 pins to put both clocks in the same DQ group, I will have to use a DQ group that does not have DQ/DQS pins.  Can I split the 2 clocks into 2 different DQ groups? If I want to put the two clocks in a separate DQ group that I also use for other signals such as address and odt, does it matter where that group is located?  My question is probably a little confusing; I can clarify any part if needed.  Thank you for you help!

[Altera_Forum]

Hello, 

 I am trying to use 2 x16 DDR2 chips and combine them as 1 x32 DDR2 using the HP DDR2 IP. I am using differential DQS and have one CK/CK# pair per chip.  In the emi_plan_pin document (version 2.0) page 2-16, it says that if I use diff DQS, I have to put the first clock pair in a pin with DIFFIO_RX or DIFFIN and the second clock in a pin with DIFF_OUT in the same single DQ group.  In the Arria II package I am using, each x8 group allows a max of 12 pins to be used. So, 8 DQ + 2 DQS is 10 pins leaving 2 pins for other assignments. Since I need 4 pins to put both clocks in the same DQ group, I will have to use a DQ group that does not have DQ/DQS pins.  Can I split the 2 clocks into 2 different DQ groups? If I want to put the two clocks in a separate DQ group that I also use for other signals such as address and odt, does it matter where that group is located?  My question is probably a little confusing; I can clarify any part if needed.  Thank you for you help!

[Altera_Forum]

I believe the only requirement is that you place the CK/CK# pair in the same DQ group and follow the rules you've already outlined about which pins they can reside on. I do not believe there is any requirement for them CK/CK# pins to be located in the same DQ group as your actual DQ/DQS pins. 

 Try it in Quartus. If you get it wrong, it should give you an error.  Jake

[Altera_Forum]

Jake, thank you for the feedback! 

 What I ended up doing was put both CK/CK# pairs in one x4 DQ group. Quartus does no complain about it (but then again, it did not complain when I had them in different DQ groups.) What is confusing in the Altera documentation is when they say "the same DQ group", it is not clear if they meant the same DQ group as the DDR2's DQ/DQS signals associated with that CK/CK# pair or that the CK/CK# pairs share "a" DQ group.  Once the layout is done, I should be able to plug in the trace model and I will have a better TimeQuest analysis. I will post the results then.  Thank you for your help.