Sdram access in HDL and Nios II

[Altera_Forum]

Hi 

 I'm fairly new to FPGA programming. I would like to use the onboard sdram memory of my DE2-70 board to pass data between c++ software, running on a Nios II cpu and a verilog component. What would be the most ideal way to do this (performance and usability taken into account)?  I'm already able to include a sdram controller using the SOPC builder and accessing it in C++ by directly writing to the sdram memory address I found in the SOPC builder. What I don't see is how I can access this data from a custom verilog component (in this case for writing an array of pixels to an electronic sign.  Any help is much appreciated. Thanks

[Altera_Forum]

You need to add an Avalon MM master interface to your custom component.

[Altera_Forum]

Thanks for your reply. 

 In that case, would I need to change the way I access the sdram memory in c++. Or can I just keep directly addressing the base pointer? And can I read/write to the sdram memory from both locations (nios and custom ip core) without worrying about collisions or data corruption during simultaneous operations?  Thanks

[Altera_Forum]

You don't have to worry about simultaneous accesses but you do have to worry about cache coherency and data hazards. If your hardware needs to access blocks of memory at a time then I recommend using a DMA engine to move the data to/from memory and your accelerator so that you don't have to implement it yourself. 

 More details about what you are attempting to do in hardware will probably result in a less generic answer.

[Altera_Forum]

Thank you. Data coherency is indeed important for my application. The C++ application on Nios II serves as a slideshow player for text and images. Everytime a new frame needs to be displayed it pushes this pixel data (48 x 112 pixels of 8 bits) to the sdram memory. The custom ip core I will write should than display this data on an electronic sign using the GPIO port. 

Maybe I'm a little naïve but couldn't I just reserve 1 bit to indicate a new frame has to be displayed? This bit could be set to 1 by the c++ application and to 0 by the ip core (when the frame has been written).

[Altera_Forum]

If you only have 48x112 bytes of image data, it is probably easier to use dual-ported on-chip memory inside the vhdl component and write directly to it from your C code. That way you only have to write the simpler Avalon slave interface.

[Altera_Forum]

That's interesting. Could you maybe tell me more about how I can do this? 

I don't know how to create dual port on chip memory. I only have used the SOPC builder to add regular on chip memory for a Nios II cpu. Thanks.

[Altera_Forum]

I hope I understood this correctly: 

 I can define a dual port memory core (like in the file I attached) and add an Avalon slave to one of the two ports?  Through this Avalon slave I can than access the memory from within the Nios II? Trough the second port I can also access the memory from within my custom IP core?  Is this correct? What I don't understand is how I can add the ram core to the SOPC system and still connect to the other available port from another custom ip core. I'll just get started and see where it takes me.

[Altera_Forum]

You create a component that has the on-chip memory inside it (not the on-chip component that appears in SOPC Builder). If you want a verilog example shoot me PM with your email address and I can send you something I'm working on that does this.

[Altera_Forum]

i have made avalon master components and my own DMA access to an offchip SDRAM using my avalon master and an SDRAM controller. Its not very hard especially if you are just doing writes and no reads. Reads take a little bit more work.  

 You can also have the nios hooked up as a master to the sdram controller. You can have to masters hooked to one slave unit and then you can set the arbitration priority in sopc builder so that either nios or your component have acess priority.   Also as they told you above for really small amount of memory, you could probably just use an onboard memory hooked up as a slave in SOPC or embed it within your component.

[Altera_Forum]

Ok, thanks again for the replies. I think this evening I'll try the custom dual port memory approach and keep the sdram approach as a backup :rolleyes: 

I'll report in this thread.

[Altera_Forum]

It seems I've been able to create the dual port memory using the megafunction wizard. 

But how do I connect one end to my custom ip core and the other port via a avalon slave to the nios. I tried adding it in the SOPC builder but I couldnt understand the connections between the dp ram and the avalon slave interface.

[Altera_Forum]

this is a bit hard to explain over the web, but its pretty easy to do. if you put your mouse over the slave port on your memory, you should see buss lines show up. You need to click the node to connect that particular slave to your master you want to be connected to it.  

 You can more than one master hooked to the same slave. There is an arbitor inserted for you by the avalon fabric. hope that helps.

[Altera_Forum]

@ Zwok 

 Could you please help me in this .. How did you write the pixels from the Nios II C code into the SDRAM?  What C code did you use?  Thanks