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Does internal CRC error detection effect design?

Altera_Forum
Honored Contributor II
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Hello, I am using a cyclone II device, & am interested in using the internal CRC error detection option, for higher reliability. My question is, if this option is enabled, does it effect the user design operation in anyway? or is this a parallel process to the user design?

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Altera_Forum
Honored Contributor II
551 Views

The altera documentation says that it reduces the fmax of the design.

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Altera_Forum
Honored Contributor II
551 Views

 

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The altera documentation says that it reduces the fmax of the design. 

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Hi, thanks for the reply, but what does that exactly mean? The highest clock frequency that you are allowed to use? When I go to enable the bit in quartus it says "enabling this slows the performace" or the like. It kinda sounds like it affect the design.
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Altera_Forum
Honored Contributor II
551 Views

As far as I'm aware of, the only documentation statement related to possible performance reduction with error detection CRC is in the description text of the respective tab in the Quartus software:  

 

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Using this feature in Stratix, Cyclone, or Stratix GX will cause a reduction in device speed. 

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My personal guess: The statement is simply incorrect.
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Altera_Forum
Honored Contributor II
551 Views

I guess you could loosely interpret what quartus says "Using this feature in Stratix, Cyclone, or Stratix GX will cause a reduction in device speed", into what amilcar said: "it reduces the fmax of the design." well, very very loosely.

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Altera_Forum
Honored Contributor II
551 Views

My guess is that the CRC circuitry has fmax1 

Your system will have fmax2 

 

If your fmax2 is bigger than fmax1, using crc will degrade your system to fmax1 

 

If your fmax2 is smaller than fmax1, using CRC will not degrade your system performance, you will still only get fmax2. 

 

This is MY personal interpretation.
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Altera_Forum
Honored Contributor II
551 Views

I agree with FvM that the Quartus statement doesn't make much sense. amilcar's interpretation might make a little bit more sense, but IMHO, not really too much. 

 

The CRC error logic uses its own clock, has a configurable clock divisor, and it is connected to user logic only optionally. So, in the worst case, it would affect performance of that user logic connected to the CRC block. If at all. 

 

SIII handbook has this sentence: 

 

 

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Using CRC error detection for the Stratix III family has no impact on fitting or performace of your device. 

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