Cyclone III EPC120F484C8 LVDS speed

[Altera_Forum]

Hi, 

 I'm planning to use a Cyclone III EPC120F484C8 to read the data from an ASIC. The ASIC has 50 parallel output bits (25 LVDS pairs read using clock A, and 25 more using clock B) at a continuous frequency of 200MHz (50-bits of parallel data every 5ns). I was wondering if I can read the data using this FPGA?   Looking at the Switching Characteristics chapter (chapter 1 Table 1-31) it says that is can achieve 402.5MHz, is that true? Also, the High-Speed Differential Signaling in Cyclone Devices (chapter 9 Table 9-7) says 275MHz. Can anyone help me understand this a bit better?  Any advice will be more than appreciated.

[Altera_Forum]

You didn't read the manual thoroughly. 275 MHz restriction is for emulated LVDS only. But it would be still above 200 MHz, so I wonder what you are actually asking for? 

 The said device has a sufficient number of differential input pairs, everything else is a matter of detail design.

[Altera_Forum]

I've been reading the documentation, but perhaps you can point me to the right chapter/section. I have a small daughter card with a Cyclone III EPC120F484C8 and enough LVDS I/Os. As I said, the FPGA is only collecting the data from 50 LVDS pairs in parallel (no serialization). Every clock cycle i need to collect the data on the 50 LVDS pairs. The clock runs at 200MHz. I'm just trying to make sure the FPGA can do the job.

[Altera_Forum]

Yes, the maximum interface speed is 402 MHz. But clocking the datapath at 200 MHz already restricts the complexity of logic and arithmetic operations, that can be performed in a single clock cycle. But that's a matter of core performance rather than I/O speed.

[Altera_Forum]

OK thanks. Essentially I need to collect the data and put it in some sort of memory (e.g. FIFO). Perhaps I need to look into some pipeline scheme if the 200MHz is too fast. I don't need to do a lot of operations on the data, is mostly storage to then send it to a PC via a USB interface.