Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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combinational delayline

Altera_Forum
Honored Contributor II
‎10-22-2010 09:30 AM
1,036 Views

Hi, 

hope someone knows the answer to this one. 

The basis of my design is a compinational delayline made from buffers from an input pin to an output pin with each buffer tapped into the D of a Dtype reg. 

I have 4 delaylines and they must be of the same timing. I have an empty stratix III to perform this starting point where I will then lock the cells and routing for the rest of the design. 

Try as I may I cannot get these 4 circuits to be the same as the router seems to arbitarly place the design. How can I tell the router that these are critcal paths. There are no clocks or set and hold timing as this delay is purely combinational. 

 

Thanks 

Robert
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Altera_Forum
Honored Contributor II
‎10-22-2010 11:09 AM
291 Views

You could try by specifying an 'impossible' Tpd from input to output. The router will try its best.

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