UART in Verilog, testing in Modelsim/Quartus

[Altera_Forum]

Hi, 

 I need some help with UART use on Bemicro board. I have a small verilog design and want to debug it. Hence I am planning to send some data over UART to see on computer (I belive thats easiest way to debug my design?). I dont want any processor in my design. So, is there a reliable and simple UART verilog core altera gives? (to speed up my work ! ! !).   And even if I write a UART interface on FPGA side, how to I test it? does modelsim help me read TxD and RxD pins (from UART) on FPGA so that I can send some data and receive on my computer?  There are two questions here. I am really struck with UART in my work. Any help here is really appreciated.  Thanks, Sirisha

[Altera_Forum]

Hello, you can use Signal Tap.

[Altera_Forum]

You can/should defer debugging with SignalTap until you really run into trouble. 

The approach is to first simulate. With the internal simulator (before QII 10.0) it was easy, you just copied the waveform of the TxD output, as generated by the simulation, onto the RxD input waveform and then ran a second simulation to see whether reception runs OK. I don't have experience with ModelSim (yet ...) but there's another trick you can use: connect the TxD output back into the rxd pin of the UART function, so you don't need to hassle around with copying waveforms or generating a complicated testbench. Maybe add some logic to switch either to the external RxD pin or to the internal loopback of TxD.