Help about Verilg error 10663

[Altera_Forum]

I got some source code, if I directly compile it without any change, the compilation is successful. If I make any change, even just delete one space in the comments part, and compile it again, it will show the Error (10663): Verilog HDL Port Connection error. I checked the code, and found it uses a lpm_mult module, in which the output "result" is defined as wire type, but in the top-level entity it's defined as reg type. If I change the reg type to wire type and re-compile, it will be successful.  

 Any one could tell me what could be the possible reason? Why the original source code can be compiled successfully even the data types not match? The source code is written with Verilog.  Thanks ahead.

[Altera_Forum]

Can you post the original code?

[Altera_Forum]

Hi, thanks for attention. But the source code is too long to put it here. If possible could you give me some general idea how this could be done? Is there any trick through which we can manage it?

[Altera_Forum]

According to Verilog port connection rules, the sink of a port assignment has to be of the net type. In so far, it's a syntax error to connect an output port to a variable type (e.g. a reg). So the only dubious point is, that the syntax error doesn't show from the beginning.