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hi,
I'm using a Startix IV FPGA (EP4SGX180FF) and I have 3 questions regarding IO standards, for PLL input and output pins, and for regular IO's: 1. what IO standards does the refclk inputs accept (for example "clk0n" and "clkop" pins)? for example: does it support LVDS input, even if I set the VCCIO of that bank to 1.8V (for using it's IO's as LVCMOS-1.8)? same question if I set VCCIO=3.3V. 2. same question for the dedicated clock output pins at relevant banks, marked as "clkout0p" and "clkout0n" for example. 3. I use one bank as SSTL-1.5 satndard (for DDR3), with VCCIO=1.5V, VCCPD=2.5V and VREF=0.75V. is it possible to use IO's from this bank as LVCMOS 1.5V input/output? can I mix voltage referenced (SSTL) and non voltage referenced (LVCMOS) standards on same bank the same time? thank you!Link Copied
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anyone? ...
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