how to write test bench to see internal signals in ModelSIM-Altera

[Altera_Forum]

Hi, 

 I've created a small microprocessor, with internal register, counter, ALU, ... and i want to see the internal value of some of them in the modelsim simulation (RTL and gate level). It was very easy with the previous version of simulation, but i don't see how to make it with a test bench file.  There is a solution to add new signals in the top-level file, but this solution is not clean. I supposed that it exist a more intelligent solution and i ask for your help to find it.  To be more complete : In my example, in the top level file (microP vhdl file), i have 3 instances of the register component (inst_reg_A, inst_reg_B and inst_reg_Adr). The register component include a signal 'reg'. So my question is how to specify in the vhdl testbench file that i want to see the inst_reg_A.reg value, inst_reg_B.reg ..   Thank's  EON

[Altera_Forum]

Usually, ModelSim will allow you to navigate through the tree of instances and add any internal signal you like to the waveform display. 

 With ModeSim PE, I've came across situations where it would optimize away signals from RTL simulation. But I never had that issue with ModelSim-Altera.

[Altera_Forum]

Hello, 

 Effectively, to solve my problem i learn how to use ModelSim-Altera and i found how to add internal signals in the simulation.   Nevertheless, if there is solutions in VHDL to specify it, i think that it will be more satisfying.  Bests regards to all,  EON

[Altera_Forum]

i don't know about adding them in HDL without porting everything to the top 

 what i usually do is use NativeLink to generate the simulation script once, then i add some internal signals i want to observe right into the Quartus generated .do file. when you add signals to the wave using ModelSim GUI, it will show the command it used in the console window. you can copy and paste that into the .do file. you can also adjust the signal radix and display format in the .do file  after you get a working .do file, you can go to NativeLink setup and tell Quartus to use the simulation script that you edited. as long as you don't add or remove any HDL files in the project, this simulation script should good to use

[Altera_Forum]

In Verilog you should be able to access internal signals using UUU.sig_name notation. 

 A similar way should exist for VHDL

[Altera_Forum]

Also be carefull when you run a gate level simulation. 

The name of your internal signals can change unless you don't use the 'keep' or 'preserve' attribute.  The 'keep' attribute, however, will prevent the optimization of the logic that refer to the 'kept' signal.  Hope this helps.

[Altera_Forum]

If you need to drive the internal signals the followin post could be useful. 

  http://www.alteraforum.com/forum/showthread.php?p=96917#post96917  Don't know if the link works. However you can search a post entitled 'Verilog simulation' posted by myself.