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Hi all,
Currently I am running NiosII UDP Offload reference design from (http://www.alterawiki.com/wiki/nios_ii_udp_offload_example). I believe during initialization, both MAC registers and PHY registers should be configured from NiosII. Can anybody tell me where are the piece of codes that perform these initialization? Thanks!Link Copied
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It is done in the TSE Interniche driver. You can find it at:
<quartus install dir>\ip\altera\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet\UCOSII\src\iniche- Mark as New
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Thanks, Dai!
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