Cyclone III, read write errors with True Dual Port M9K Memory

[Altera_Forum]

Hello Everyone, 

i am having some problems with using M9K block on Cyclone III, following is the detail of my system configuration, and the workout i have done till now and their results, if any one understand this issue, please contribute your ideas. also, the timings of reading writing have been honored according to the Altera Memory Handbook.  My System:  a custom designed system containing an ARM7(56MHz) connected to 16MB external ram and shares the data and address bus with FPGA as-well, this is then connected to an external connector which is capable of connecting to an embedded x86 system(with LPC Port 33MHz).    Problem Description:  I am using a True Dual Port Ram with dual clock in my core, and since the beginning i am having problems to read and write the dual port ram. i would like to give a brief description of the test cases i have gone through,    1.. Dual Port ram megacore implemented in my design, and there were a lot of read and write errors, one constant error on address 0x00 was that a data 0xcc is presented always on read and this location was not writable aswell. many other address locations have the same behavior but with different data in them.    2.. Dual Port Ram Megacore ONLY, created a new project that contains only a dual port ram which was then connected to output ports of fpga (internally). and the result was that i can read and write every address BUT, which i read these addresses again, the data has been replaced by some other data, and this replacement of data has a very strange pattern, for example, i write first 5 addresses of the ram with some data:    Write Data  Address: 0x00 Data: 0x05  Address: 0x01 Data: 0x04  Address: 0x02 Data: 0x03  Address: 0x03 Data: 0x02  Address: 0x04 Data: 0x01    now when i read the data i get the following results,    Read Data:  Address: 0x00 Data: 0x03  Address: 0x01 Data: 0x02  Address: 0x02 Data: 0x01  Address: 0x03 Data: 0x02  Address: 0x04 Data: 0x01    if you note for instance the address 0x02 and 0x04 then you see that the data of address 0x04 has been written to the data or address 0x02 and the original 0x02 data is lost.    note in above cases the writing and reading was done by the ARM micro controller, with clock frequency of 56MHz.    3.. FPGA Replacement: i then replaced my current cyclone iii (EP3C16Q240C8n) with another cyclone iii (EP3C10E144C7N), and implement the same scenario, the project file that only contain true dual port ram. and this time the results were a little bit different, see below,    DATA READ  Adresse 0x00 Data 0  Adresse 0x01 Data 9  Adresse 0x02 Data 9  Adresse 0x03 Data 8  Adresse 0x04 Data 7  Adresse 0x05 Data 0  Adresse 0x06 Data 0  Adresse 0x07 Data 0  Adresse 0x08 Data 0  Adresse 0x09 Data 0  Adresse 0x0a Data 0  Adresse 0x0b Data 0  Adresse 0x0c Data 0  Adresse 0x0d Data 0  Adresse 0x0e Data 0  Adresse 0x0f Data 0  Adresse 0x10 Data 0  Adresse 0x11 Data 9  Adresse 0x12 Data 9  Adresse 0x13 Data 8  Adresse 0x14 Data 7  Adresse 0x15 Data 0  Adresse 0x16 Data 0  Adresse 0x17 Data 0  Adresse 0x18 Data 0  Adresse 0x19 Data 0  Adresse 0x1a Data 0  Adresse 0x1b Data 0  Adresse 0x1c Data 0  Adresse 0x1d Data 0  Adresse 0x1e Data 0  Adresse 0x1f Data 0      and now here you can see with the read cycle that after every 16 bits the data is repeated or replaced with the original.    now what should i suspect, the megacore, or the FPGA, because the outputs of the same core are different on two different fpga's, is there a chance that there is a silicon defect? as i have tested two chips of cyclone III (EP3C16Q240C8n) and they both have same output.    i also have tested the reading and writing of data from a slow system, the old 8051 controller, with a very slow clock, and the results were the same, i.e. wrong data read.    i also have read the Altera Errata for the Cyclone III device family and also tried to do the workarounds mentioned there and nothing changed.    i would be looking forward for a quick support.  Thanks alot for your time.

[Altera_Forum]

This is definitely a timing problem. 

I think you are reading memory data before addr lines have set up (then you get data from a different address) or before data lines have set up. Have you tried to add wait states on memory access: usually this fixes the problem in such cases. Are you sure the data is written correctly into memory and the problem is on the read side?  Regards

[Altera_Forum]

Without any details about the RAM interface at the processor side, we could only guess about possbile reasons. I guess, there are many ways to create an incorrect RAM timing.

[Altera_Forum]

Hi all,  

 I think that I have the same problem, so, how can I "add wait states on memory access" ?  I'm a just a novice with Quartus. So please explain to me, slowly slowly.  Thanks.