How quick to go into High-Z?

[Altera_Forum]

I am using an FPGA on a parallel bus shared with about 7-8 other devices, mostly ADCs and DACs. I am interfacing the FPGA with the code below to only send data to the Microcontroller when chip-selected, read is low, and addressed to.  

 module tri_state_out(chip_sel,in,out,address,rd);  input [15:0]in; input chip_sel; input rd; input [2:0]address; output [15:0]out; assign out = (chip_sel==0 && address==0 && rd==0) ? in : 16'bzzzzzzzzzzzzzzzz; endmodule   I finished the design and the FPGA works great, however now I am having some issues with some of the other devices on the parallel bus.    Is there any delay assosiated with going into hi-z? Any advice why this should or should not work?

[Altera_Forum]

The logic should work, it's generally a good idea to operate the output driver asynchronously. Some delay (several ns) is involved with any FPGA logic of course, I don't expect that it's causing problems at usual bus speeds. If address changes immediately before rd get's active, glitches may occur, but they must not necessarily cause problems. The output drive strength should be adjusted to the bus load and speed requirements. 

 P.S.: 7-8 devices is quite a lot, it may be a problem of additional capacitive bus load by the FPGA.

[Altera_Forum]

OK thanks for the tips. I still havent had the chance yet to scope anything out, but my latest hunch is that things are not initializing properly.  

 I think the FPGA is coming up way before the DSP and taking control of the parallel bus when it shouldn't be. (If I program the Serial Flash Device and reboot both FPGA and DSP I have issues, however if I clear the FPGA then reboot and then program the FPGA using JTAG while the DSP is already up and running,,,no issues).   What is the best way to delay the FPGA from starting up until the DSP is up and running?