Backtrace while converting sof file to pof file for flash programming

[Altera_Forum]

I am using the NIOS II IDE to program a flash EPCS4 device with time-limited configuration data for my Cyclone II design.  

 I get the following error:  Info: Command: quartus_cpf --convert --device=EPCS128 H:\ee3grp\quartus\1\test_time_limited.sof test_time _limited.pof File H:/ee3grp/quartus/1/test_time_limited.sof contains one or more time-limited megafunctions that suppo rt the OpenCore Plus feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details. Info: SRAM Object File H:/ee3grp/quartus/1/test_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00A2 Internal Error: Sub-system: PGMIO, File: /quartus/pgm/pgmio/pgmio_flash_mapping.cpp, Line: 3696 ranks->size() > 0 Stack Trace: 0x88EC26 : (MSCTF) End-trace  A quick google search shows nobody else with this error :-(. Any ideas?

[Altera_Forum]

Hi, when you have a time-limited megafunction in your design, it is not possible to generate POF file. You can only use SOF and download it by JTAG to your FPGA.

[Altera_Forum]

Why is there a "flash programmer" menu item in the NIOS ide then? 

 Also, I was under the impression that "time-limited" means that when programmed via JTAG the device works for unlimited time, but when programmed by config flash chip it is time limited to 1 hour - am I incorrect?  My use case is for a portable device, so I'm looking to be able to turn it on and use it without a super long jtag cable...

[Altera_Forum]

When you purchase the IP core, you will get rid of time-limited "feature" and then you will be able to generate the POF. Until then, I am afraid you will have to download using JTAG. After downloading you can disconnect the cable and the core will function for one hour, but there is no way how to load it to the flash. 

 Well, it is quite obvious, because then you could just add some watchdog to your board that will reload the fpga after one hour and you would get the function of the ip-core for free.

[Altera_Forum]

I always considered a bit silly that Quartus refuses to make a POF for Opencore evaluation.  

   --- Quote Start ---  Well, it is quite obvious, because then you could just add some watchdog to your board that will reload the fpga after one hour and you would get the function of the ip-core for free.  --- Quote End ---    True, but if you insist, you can do a similar hourly reload through JTAG.

[Altera_Forum]

Well yes, indeed, but have you tried that? I suppose that you would find that the design is not working at all. The way I would do the evaluation of the IP core (and I believe that Altera did it that way too) is to include non-functional core into the SOF and then, after the core is downloaded, start the function of the core through the ByteBlaster. So if you do not use the Quartus to download the FPGA, the design will remain non-functional.

[Altera_Forum]

I didn't try. May be it won't work without Quartus. But if you insist, there are situations where you might be able to use tethered mode in production. Any evaluation method always has some risk of ilegal usage. 

 Anyway, my point is that the idea of not allowing a POF, isn't too smart as a security measure. There are valid evaluation situations, as the case of the OP here, where a POF is needed. And there are invalid uses, even with just a SOF.  Bottom line is that Altera and its Opencore partners, as sellers, probably don't benefit from this.