Signal assignment not working correctly

Altera_Forum · ‎11-17-2010

Hi,

I am trying to save an input message in a signal or variable....and if found that it is all the time i have an output ZERO

CODE:

------------------------------------------------------------------------

process(clk, message_in)

variable j : integer :=0 ;

variable i : integer :=0 ;

variable tmp: std_logic_vector(107 downto 0):=(others => '0');

begin

if (clk'event and clk='1') then

if (i=0 and j<=107)

If ((message_in(i +1) /= message_in(i+2)) then

tmp(j+1) := message_in(i+1);

tmp2<= tmp;

i:=i+2;

j:=j+2;

else

.........

end if;

elsif (j>107) then

tmp(12 downto 0) := message_in(12 downto 0);

tmp2<= tmp;

end if;

end process;

message_out <= tmp2;

---------------------------------------------------------------

using modelsim... I got only in the message_out the last 13 bits )which coming from the last if statement) and the remaining are zeros...

also when i check the internal signal (tmp), i find that it is all the time zeros and the last 13 bits are dont care.

this is not the exact code...this is just for make it simple to trace it.

The counters i and j are wokring correctly but the bold line in the code is not workingcorrectly

So any ideas?

Altera_Forum · ‎11-17-2010

Hi,

First, use synchronous design : use process(clk) (no process(clk, message_in) :-( )

It will be a good point.

--- Quote Start ---

the counters i and j are wokring correctly but the bold line in the code is not workingcorrectly

--- Quote End ---

You should post all the process. The first time i and j may work as you expect. Are i and j reseted to 0 after j=108 ?