MaxPlus 2: compiling errors

Altera_Forum · ‎11-20-2010

Hello everyone, i am berni69 and I'm studing telematics with our software, but like all the begginers in a new field, i have some mistake's programming in vhdl. For this reason the compiler show me errors that i could solve, all except one.

I want you help me if it's possible. Thanks, now I will paste my code:

library ieee;
USE Ieee.Std_Logic_1164.All;
Entity mod_tr IS
   Port (Data: IN Std_Logic_Vector(3 Downto 0);Recepcio,Tr,Clk,Start: IN std_logic;
   Transmissio: OUT std_logic; Reg_Entrada: OUT Std_Logic_Vector(3 Downto 0));
END Mod_Tr;
Architecture Comportament OF Mod_Tr IS
--signal: s0,s1,clr,qm,qn,qo,qp: bit;
signal clr: std_logic;
signal contador: integer range 0 to 4;
BEGIN
process (start,clk,clr)--contador
   variable n: integer range 0 to 4;
begin
   n:=contador;
if clk'event and clk='1'then
   if start='1' or clr='1' then
      n:=0;
   elsif contador/=4 then 
      n:=n+1;
   elsif contador=4 then
     clr<='1';
   end if;
end if;
contador <= n;
end process;
process (clk, clr, data, tr, recepcio)
variable shift: Std_Logic_Vector(3 Downto 0);
begin
if  clk'event and clk='1'  then
if  clr='1' then
shift:=data;
elsif  tr='1' then
--transmitim=> desplaçament a la dreta
 shift(0):=shift(1);
 shift(1):=shift(2);
 shift(2):=shift(3);
 shift(3):='0';
elsif tr='0' then
 --rebem => desplaçara  l'esquerral
 shift(0):=recepcio;
 shift(1):=shift(0);
 shift(2):=shift(1);
 shift(3):=shift(2);
end if;
end if;
reg_entrada<=shift;
transmissio<= shift(0);
end process;

In the first proccess i get the error:

"else clause following a clock edge must hold the state of signal n"

The line is:

if clk'event and clk='1'then

Lot of thanks!

Altera_Forum · ‎11-20-2010

The error message isn't fully correct, because there is no else clause to the clock edge condition. Quartus gives a better understandable message.

--- Quote Start ---

Error (10818): Can't infer register for "n[0]" at mod_tr.vhd(22) because it does not hold its value outside the clock edge

--- Quote End ---

The code can be compiled, when you change it like this:

process (start,clk,clr)--contador
  variable n: integer range 0 to 4;for the 
begin
if clk'event and clk='1'then
   n:=contador;
   if start='1' or clr='1' then
      n:=0;
   elsif contador/=4 then 
      n:=n+1;
   elsif contador=4 then
     clr<='1';
   end if;
   contador <= n;
end if;
end process;

You can write the same logic without the variable n. I don't think, that the code works as expected, because the signal clr is only set but never reset.

Altera_Forum · ‎11-20-2010

Ohh thanks!! with your help i solved my problem!!