SSRAM Verify failed after adding custom components in SOPC Builder

[Altera_Forum]

I created a system based on the template for the Stratix II Nios Kit. I took the SDRAM away since I don't have a license for that IP Core. I intended to use SSRAM since it's a small project. I compiled in quartus and programmed the FPGA then created a hello world application in Nios IDE and it compiled and run ok. Now when I add custom components in SOPC Builder like PWM and ADC interface, generate, assign pins, compile in quartus, and try to compile in Nios IDE I get verify failed at address 0x01000000. 

 I configured unused pins as tristate inputs and triple check pins assignments so I don't know what could be the problem. Can anyone help me please?

[Altera_Forum]

anyone please?

[Altera_Forum]

Did you constrain the memory interface and does your design meet the timing requirements when you compile it?

[Altera_Forum]

hi i have the same problem i'm using an ssram in my design at STRatix II and the rpject compiled successufilly but when i use the NIOS IDE with the project of hello world the project build with no error but when i run it i have this problem 

 Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x00801040: verified Initializing CPU cache (if present) OK  Downloading 00400000 ( 0%) Downloaded 53KB in 0.9s (58.8KB/s)  Verifying 00400000 ( 0%) Verify failed between address 0x400000 and 0x40D073 Leaving target processor paused  plz some one can help me

[Altera_Forum]

Did you constrain the memory interface and does your design meet the timing requirements when you compile it?

[Altera_Forum]

what do u mean by memory interface and yes when i compile i have timing requirements

[Altera_Forum]

By memory interface I mean the FPGA pins that are connected to the memory. You should check that your timing contraints file is correct on those signals.

[Altera_Forum]

i chek right now rtl viewer this i the schematic

[Altera_Forum]

where can i find it i'm new n this

[Altera_Forum]

You need to familiarize yourself with Timequest. There is a good user guide on the wiki (http://www.alterawiki.com/wiki/timequest_user_guide).

[Altera_Forum]

thks but i'm limited with time

[Altera_Forum]

There is unfortunately no "quick and dirty way" to do this. If you don't have a proper timing, your design may run into problems. Are you using a kit? Aren't there example designs that you can use?

[Altera_Forum]

yes i use stratix ii and i have examples

[Altera_Forum]

Then you should start with the examples. If they work and your design doesn't, look for differences between the two, especially around the memory controller and the timing requirements (.sdc files).

[Altera_Forum]

the problem is that also when i run with examples like full featrued i have also the same problem

[Altera_Forum]

are you sure you put the correct .sof file and are compiling with the correct .sopcinfo description? Check also that the address used when downloading the software (0x400000 in the example you gave) is the correct one for your main memory.