Test Bench Settings

[Altera_Forum]

Dear all, 

 trying to understand the form "Edit Test bench Settings" that you reach when, in QuartusII, go Settings -> Simulation -> Test Banches -> New.   In the form you have to specify "Test bench name" and "Top level module in test bench".   This is enough to run both RTL and Gate Level simulation.   Further, you find a check box named "Use test bench to perform VHDL simulation". If you check this you've to specify the design istance name in test bench.   I found that if you ask to generate the VCD file you have to specify the above cited field and a textbox in the VCD file settings.   1) Can you tell me which is the use of the checkbox "Use test bench to perform VHDL simulation"?   2) I'm using Verilog and QuartusII web edition. Multilanguage simulation shouldn't work. Why it cites VHDL?   3) Which is the connection between the above cited checkbox and the VCD file?   Thx.

[Altera_Forum]

Dear all, 

 a small update.   Reading the manual it says that "Use test bench to perform VHDL simulation" must be checked for Gate Level simulation.   However, even without this checked I can execute Tools -> Run EDA Simulation Tool -> EDA Gate level simulation  and see delays in my simulated circuit.   Am I doing something wrong? Is it a Gate Level simulation what I'm running or something is missing in it since I do not check the "Use test bench to perform VHDL simulation" checkbox?   Thx.

[Altera_Forum]

No answer.... 

 Probably the topic is not familiar to most of you.   I wonder if some of you that uses Verilog can tell me if use to set the "Design Istance" name in the test bench settings or leaves it to N/A.   Thx.