Hi:
here is a warning just like:
Warning (10235): Verilog HDL Always Construct warning at CurCtrl.v(559): variable "CurfbkA_o" is read inside the Always Construct but isn't in the Always Construct's Event Control
the veriable is not sensitive veriable,i do not care the value.for example:
always @(posedge clk)
begin
a <=CurfbkA_o;
end
who can tell me how to cut this warning.thanks!
