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For an external clock CLKIN from a CYCLONE III clock pin, do I have to instantiate altclkctrl explicitly in VHDL so that CLKIN can be routed to global clock network? or Quartus II will do it automatically and implicitly?
What about an internally generated clock - from a frequency divider/counter, not PLL?Link Copied
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Anyone can help? :confused: Thanks in advance.
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it will be done automatically. check your Fitter report in the Resources section to see what Quartus has promoted to Global signals. you can also use the Assignment Editor to place specific signals onto Globals
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Thank you, thepancake:)
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