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Problem with MMU with a custom board

Altera_Forum
Honored Contributor II
1,073 Views

Good Afternoon. 

 

Hello, I have an custom FPGA board which have an CycloneII and a SDRAM of 32MBit 

 

I have been developing without MMU for a long time, but I come to the need of having C++ an pthread support simultaneousness, which for what I have read in the forum is only possible with the MMU version (the no-mmu hang up when you link pthread and uses C++ clases) 

 

I followed nioswiki/linux but when I boot the MMU version I get the folowing mensages: 

 

 

--- Quote Start ---  

 

[NiosII EDS]$ nios2-download -g /home/fconcha/Desarrollos/nios2-linux-new/uClinux-dist/images/zImage.initramfs.gz  

Using cable "USB-Blaster [USB 2-1.3]", device 1, instance 0x00 

Pausing target processor: OK 

Initializing CPU cache (if present) 

OK 

Downloaded 3411KB in 69.0s (49.4KB/s) 

Verified OK  

Starting processor at address 0xC2500000 

 

~/Desarrollos/Quartus_ISIS/Altera10/TEST_WITH_MMU 

[NiosII EDS]$ nios2-terminal 

nios2-terminal: connected to hardware target using JTAG UART on cable 

nios2-terminal: "USB-Blaster [USB 2-1.3]", device 1, instance 0 

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) 

 

Linux version 2.6.35-00743-ge3b9b64-dirty (fconcha@fcaUbu10) (gccUncompressing Linux... Ok, booting the kernel. 

Linux version 2.6.35-00743-ge3b9b64-dirty (fconcha@fcaUbu10) (gcc version 4.1.2)# 47 Mon Dec 13 18:41:16 CLST 2010 

bootconsole [early0] enabled 

early_console initialized at 0xe4001458 

 

 

Linux/Nios II-MMU 

init_bootmem_node(?,0x24a4, 0x2000, 0x4000) 

free_bootmem(0x24a4000, 0x1b5c000) 

reserve_bootmem(0x24a4000, 0x400) 

Built 1 zonelists in Zone order, mobility grouping on. Total pages: 8128 

Kernel command line:  

PID hash table entries: 128 (order: -3, 512 bytes) 

Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) 

Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) 

We have 16384 pages of RAM 

Memory available: 27724k/4749k RAM, 0k/0k ROM (1817k kernel code, 2931k data) 

Hierarchical RCU implementation. 

RCU-based detection of stalled CPUs is disabled. 

Verbose stalled-CPUs detection is disabled. 

NR_IRQS:32 

Calibrating delay loop... 49.35 BogoMIPS (lpj=246784) 

pid_max: default: 32768 minimum: 301 

Mount-cache hash table entries: 512 

NET: Registered protocol family 16 

init_BSP(): registering device resources 

bio: create slab <bio-0> at 0 

Switching to clocksource timer 

NET: Registered protocol family 2 

IP route cache hash table entries: 1024 (order: 0, 4096 bytes) 

TCP established hash table entries: 1024 (order: 1, 8192 bytes) 

TCP bind hash table entries: 1024 (order: 0, 4096 bytes) 

TCP: Hash tables configured (established 1024 bind 1024) 

TCP reno registered 

UDP hash table entries: 256 (order: 0, 4096 bytes) 

UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) 

NET: Registered protocol family 1 

RPC: Registered udp transport module. 

RPC: Registered tcp transport module. 

RPC: Registered tcp NFSv4.1 backchannel transport module. 

msgmni has been set to 54 

Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) 

io scheduler noop registered 

io scheduler deadline registered 

io scheduler cfq registered (default) 

ttyJ0 at MMIO 0x4001458 (irq = 11) is a Altera JTAG UART 

console [ttyJ0] enabled, bootconsole disabled 

console [ttyJ0] enabled, bootconsole disabled 

ttyS0 at MMIO 0x4001400 (irq = 10) is a Altera UART 

TCP cubic registered 

NET: Registered protocol family 17 

Freeing unused kernel memory: 2428k freed (0xc21c8000 - 0xc2426000) 

 

--- Quote End ---  

 

 

Then nothing, it just stay there forever. 

 

I use a NEEK to check and with the same kernel config (changing the Board layer files) and the kernel boot OK using the neek_web_server_mmu.zip from the wiki. 

 

Any idea of where I could start debugging. The board work fine without MMU, but I don't know where to look after this problem.
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4 Replies
Altera_Forum
Honored Contributor II
358 Views

HEllo, this seems like lack of memory? I have the same problem with a DE2 

nvm, 32mb seems ok
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Altera_Forum
Honored Contributor II
358 Views

The same reason because I compared it with the neek_web_server_mmu, because it uses 32 MB the same I got. 

 

I think that it has to do with the reset and exception vector. In the neek_web_server_mmu I see that they are FLASH and SSRAM respectibely, but in the file linux-2.6/arch/nios2/boards/neek/include/asm/nios.h they uses the SDRAM to the kernel: 

 

# elif defined(CONFIG_NIOS2_CUSTOM_FPGA) .... # define DDR2_TOP_BASE DDR_SDRAM_BASE # define DDR2_TOP_SPAN DDR_SDRAM_SPAN ....  

 

In my proyect I have the reset and exception vector in my only external RAM, could that be the problem?
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Altera_Forum
Honored Contributor II
358 Views

Maybe but as far as i know you can use external RAM. If it works without MMU it should work with MMU. 

In my project the reset vector is at the cfi flash controller and the expection at the SDRAM! It shouldnt matter throught
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Altera_Forum
Honored Contributor II
358 Views

Ok, I managed to solve the problem I put it here only for completeness. 

 

The problem in fact was produced by my memory, the clock that I were using to fed it was produced by an PLL and was in phase with the clock of the system (100MHz), and that worked fine for the NO-MMU version. 

 

But in the MMU version I had to put an delay in the SDRAM clock, which i set to -45 degrees, so the signals to the memory now have time to be set before the clock signal arrived, and then the system started to work OK. 

 

I still don't get how the MMU forced the problem, but with the delay both system work without any problem that I can see (yet). 

 

Thank for the help.
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