Can we use a differential clock input as 2 single-ended clock inputs?

[Altera_Forum]

I use a FPGA of the Stratix GX II family, EP2SGX90FF1508.  

In my design I have 3 differential input clocks on an external connector but I actually need 5 single ended clock inputs. Is it possible to use a differential input as 2 single-ended inputs? Do we need to configure something on Quartus for that?  Thanks for you help!

[Altera_Forum]

--- Quote Start ---  Is it possible to use a differential input as 2 single-ended inputs?  --- Quote End ---  Yes.   --- Quote Start ---  Do we need to configure something on Quartus for that?  --- Quote End ---  Assign a single ended I/O standard and the respective pin location for the clock signals.