Help with HIL

[Altera_Forum]

I have a Stratix III EP3SL150F1152C2 FPGA. My aim is to put the "demo_fft256_radix4" example provided by the DSP builder in the FPGA and run it to solely demonstrate high speed simulations that can be achieved by FPGA. For this I want to use HIL and put it in burst mode. From the handbook I have understood that we need input and output for the HIL. When I place input and output blocks from IO&bus library, I get a datatype error. Can someone please help me fix this. Or is there another easy way I achieve what I want to do?

[Altera_Forum]

can you post your .mdl or a screen shot of what you've wired and the error?

[Altera_Forum]

Thanks for replying. I am not able to pot the .mdl file due to size constraints. I am attaching the screenshots of my model and the error I get. What I also don't understand is how can I generate the ports for the HIL block. Right now my HIL block is just sitting on the DUT block. I want to replace that with HIL for which the HIL block needs to have it own ports. I went through the user guide couple of times and still couldn't figure out how to go about. If you could help me with these two issues (fixing the error and generating ports for HIL block) it would be really helpful. 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=3429   https://www.alteraforum.com/forum/attachment.php?attachmentid=3430   https://www.alteraforum.com/forum/attachment.php?attachmentid=3431   https://www.alteraforum.com/forum/attachment.php?attachmentid=3432

[Altera_Forum]

have you taken a look at the DSP Builder Advanced Blockset Handbook section on HIL on page 172: 

 http://www.altera.com/literature/hb/dspb/hb_dspb_adv.pdf